Half Line Cycle Research Articles

High-Efficiency Interleaved Totem-Pole PFC Converter With Voltage Follower Characteristics

High power density, efficiency, control simplification, and robustness are highly demanded for power factor correction (PFC) converters. This paper proposes a totem-pole rectifier based on the switching cell with switching frequency modulation (SC-SFM). The SC-SFM features interleaved operation, soft commutation, and resistive characteristics with continuous conduction in the input inductor. The converter operates without needing sensors and a control loop for the current. Unlike conventional solutions or some sensorless converters, the converter does not require a fast control loop to shape the current since the current naturally follows the input voltage. Only one output voltage sensor and one input half-line cycle detector are required to achieve unitary power factor and regulated DC output voltage. A detailed analysis of the converter operation, including the operating principle, mathematical analysis, a small signal model, and control method, is presented, including the differences in operation from the conventional PFC rectifier with the diode bridge. Experimental results evaluate a 1-kW prototype with different switch technologies (IGBT, SiC, and GaN).

Triple-Mode Average Current Control with Valley Current Shaping for DCM/CRM/CCM Boost PFC Converter

This paper presents a triple-mode average current control (TACC) strategy to achieve unity power factor and reduce the current stress for a boost PFC converter. The controller switches among different modes in each half-line cycle, and smooth transition is ensured by mapping of the operation region. By adaptive mode shifting, it reduces the current stress and current distortion caused by non-linear effects. With valley current shaping and comparisons, the TACC controller accordingly incorporates three control laws to adapt different modes. In discontinuous conduction mode (DCM), a variable on-time is calculated while the modulation is equivalent to PWM. In critical conduction mode (CRM), a constant on-time is derived, while the switching cycle is modified to regulate the current average value. For both DCM and CRM, the switching cycle is slightly extended to realize valley switching. Furthermore, with valley current shaping, the proposed controller reuses the CRM calculation to form continuous conduction mode (CCM) control law. To make the control laws compatible, normalized mapping and design rules are provided with respect to mode boundaries. This allows the TACC controller to automatically switch among different modes. Finally, experimental results prove the effectiveness of the controller in reducing the current stress and enlarging the preferable power range.

Adaptive Charge-Compensation-Based Variable On-Time Control to Improve Input Current Distortion for CRM Boost PFC Converter

For boost power factor correction (PFC) converters operating in critical conduction mode (CRM), charge compensation strategies are utilized to improve input current distortion. However, since massive calculations are required under complex working conditions, it is difficult to achieve accurate charge compensation with limited real-time computing resources. To solve this issue, this paper proposes an adaptive charge-compensation-based variable on-time (ACVOT) control strategy. The ACVOT controller calculates the required switching on-time by adding a fundamental value and an extended on-time. The fundamental value is adjusted by the loop compensator in each half-line cycle to provide a basic bias. The extended on-time is calculated based on partial charge compensation equation in each switching cycle to reduce the distortion. Compared with conventional digital variable on-time (VOT) control, the proposed strategy improves the input current total harmonics distortion (THD) and reduces the LUT/register resources by 54%/43% in FPGA realization. To verify the effectiveness of the proposed strategy, a 200 W prototype is built using the GaN HEMT transistor, where the THD is reduced to 1.4% at full load.

GaN-Based High-Power-Density AC–DC–AC Converter for Single-Phase Transformerless Online Uninterruptible Power Supply

This article introduces a new transformerless ac-dc-ac converter topology suitable for a high-power-density high-frequency single-phase online uninterruptible power supply (UPS) with a common neutral between the input and output ac ports. The proposed converter comprises an input power factor correction rectification (ac-dc) stage which is followed by an inversion (dc-ac) stage. The rectification stage operates in boost mode during the input positive half line cycle and buck-boost mode during the input negative half line cycle, while the inversion stage operates in buck and buck-boost modes in the output positive and negative half line cycles, respectively. The rectification stage utilizes boundary conduction mode control enabling soft-switching and allowing high-frequency operation. The inversion stage is operated in continuous conduction mode, wherein a digital controller regulates the output voltage of the converter across both resistive and reactive loads. The proposed online UPS utilizes a single (nonsplit) dc-bus between the rectification and inversion stages, resulting in a 50% reduction in dc-bus capacitance requirement compared to conventional split-bus online UPS topologies. Additionally, two battery interface solutions are also investigated which provide a trade-off between passive volume and additional switch-count. To verify the performance and control of the proposed online UPS, a GaN-based electrolytic-free 1-kVA prototype online UPS is designed, built, and tested. The prototype ac-dc-ac converter achieves a peak efficiency of 95.2% and maintains a high efficiency of above 92.3% across the full output power range. The electrolytic-free prototype ac-dc-ac converter for the online UPS achieves a power density of 26.4 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Unified Pulsewidth-Cycle Control Strategy to Achieve Mixed DCM/CRM Operation and Consistent Valley Switching for Boost PFC Converter

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion.

Flicker-Free Resonant LED Driver With High Power Factor and Passive Current Balancing

A flicker-free resonant LED driver with high power factor (PF) and passive current balancing is proposed and analysed in this paper. The proposed LED driver are composed a buck power factor correction (PFC) unit and a resonant dc-dc unit by sharing an active switch. Based on this topology, the low output current ripple can be achieved via small voltage ripple on bulk capacitor and fast voltage-mode control loop. By the charge balance for resonant capacitor, the output current of each LED string can be balanced. In a half line cycle, owing to the small voltage ripple on bulk capacitor of pre-stage output, the duty cycle of active switch is almost constant. Therefore, when the inductor current of buck PFC unit operates in discontinuous conduction mode, high PF can be realized. Moreover, as the resonance is existed between resonant capacitor and leakage inductor of transformer, the diodes in resonant dc-dc unit can achieve zero-current turn-off. Thus, the efficiency can be improved. Finally, an 82W LED driver prototype with three-output is built to verify the studied results.

Active-Clamp Resonant Power Factor Correction Converter With Output Ripple Suppression

An active-clamp resonant power factor correction converter with output ripple suppression is proposed and analyzed. It combines a buck power factor correction (PFC) unit and a resonant dc-dc unit by sharing one active switch. With another active-clamp switch, a recycling path is built to recover the leakage inductance energy of transformer, which improves the efficiency and the voltage stress of active switch. The effect of voltage ripple of dc link on output can be suppressed by fast voltage mode control loop. Therefore, low output current or voltage ripple can be achieved. With small voltage ripple across output of buck unit, the turn on time of active switch is almost constant in a half line cycle. Therefore, power factor correction can be achieved with inductor current of buck unit operating in discontinuous conduction mode (DCM). Finally, a 65W high power factor (PF) converter prototype for LED driver application with 91.08% peak efficiency and low output current ripple is built to verify the analytical results.

Topology and Control of Four-Quadrant Dual-DC-Port Dual-Buck Inverters For Semi-Two-Stage DC–AC Power Conversion

A method to derive topologies of four-quadrant dual-dc-port dual-buck inverter (DDP-DBI) is proposed in this article. A new family of DDP-DBIs is obtained by replacing one of the switching legs in a four-quadrant dual-buck half-bridge switching cell with a dual-input buck type switching leg. With the proposed DDP-DBIs, both the low voltage dc source and the high voltage intermediate dc-bus can be used as the inputs of the inverter. Therefore, in comparison with the conventional two-stage dc-ac power system, a semi-two-stage dc-ac power conversion system with reduced power losses and enhanced conversion efficiency is achieved. A unipolar sinusoidal pulse width-modulation strategy is presented for the DDP-DBI. In each line cycle, all the power devices and filter inductors only operate within half line cycle, and only one active switch is operated at high frequency. Moreover, no freewheeling current flows through the body diodes of the active switches. As a result, the conversion efficiency of the overall dc-ac power conversion system is improved. Operation principles, characteristics, modulation and control strategies of one of the proposed DDP-DBI are analyzed in detail. Effectiveness and feasibility of the proposed DDP-DBI are verified with experimental results.

A New Modulation Technique to Improve the Power Loss Division Performance of the Multilevel Inverters

Multilevel inverters (MLIs) have offered significant contributions toward the implementation of energy conversion units used in industry and renewable energy applications. However, the switching devices in MLIs are associated with power loss division problems. The pulsewidth modulation (PWM) techniques greatly influence the peak, average, and ripple values of the device junction temperature. Thermal tension in the devices may be raised due to increased power loss caused by additional switching or uneven distribution of losses due to unbalanced gate pulses. Higher thermal stress accelerates the life degradation process of the power devices, and, eventually, leads to permanent damage of the MLI. Therefore, a new loss balancing two-pole clamped PWM technique for a single-phase MLI is proposed in this article. In the proposed PWM technique, in each half line cycle, symmetrical and equal duration of nonswitching zone is placed on the two reference signals alternately. Due to symmetrical and equal duration of clamping action, the unbalanced gate pulses become balanced after each half line cycle. The proposed technique extends the reliability of the power devices by improving the loss division performance and the junction temperature characteristics. Moreover, the reduction of neutral point potential swing reduces the output total harmonic distortion. The improved performance of the proposed technique is validated by simulation in MATLAB/Simulink and experimental results from downscale laboratory prototype test platform.

A Doubly Grounded Transformerless PV Grid-Connected Inverter Without Shoot-Through Problem

As conventional transformerless PV grid-connected inverters have shoot-through problem and common mode leakage current issue, a doubly grounded transformerless PV grid-connected inverter is proposed. The proposed inverter consists of a buck converter and a buck-boost converter, which operates at positive and negative half-line cycles, respectively. There is no shoot-through problem in the proposed inverter, so dead-time in gate signals is not required. As grounds of the PV array and the grid are shorted, the common mode leakage current can be eliminated. No current flows through the body diodes of switches, so there is no reverse recovery issue of the body diodes of switches. Only one switch operates at high frequency in each half-line period, so efficiency of the system is improved. Operating principle of the proposed inverter is elaborated in detail. The control strategy is given. The control method is simple and the grid-connected inverter is a single-stage system in each half-line cycle. Loss calculation and example is given in detail. Finally, simulation and experimental results of the proposed inverter validate the theoretical analysis.

Quasi-Fixed Switching Frequency Control of CRM Boost PFC Converter Based on Variable Inductor in Wide Input Voltage Range

With traditional constant on-time control, the switching frequency variation range of critical conduction mode boost power factor correction converter is large during a half line cycle, not to mention the wide range of input voltage's rms value. For this issue, this article puts forward a quasi-fixed switching frequency control, which combines the variable on-time and variable inductor technology together. Furthermore, a lower output voltage ripple and a higher efficiency are obtained. In spite of the power factor decrease, the input current harmonics still satisfy the IEC61000-3-2 Class D limits. The detailed theoretical analysis and experimental results are presented in this article.

Slow-Scale and Fast-Scale Instabilities in Parallel-Connected Single-Phase H-Bridge Inverters: A Design-Oriented Study

This paper reports the slow- and fast-scale instabilities in the parallel-connected single-phase H-bridge inverters and discusses the two types of instabilities from the practical design viewpoint. Simulations show that the slow-scale instability which occurs in the whole line cycle is a type of global instability, whereas the fast-scale instability which occurs around the middle time of each half-line cycle is a type of local instability. In order to reveal the mechanisms of the slow- and fast-scale instabilities, theoretical analyses are carried out through the derived averaged model and discrete-time model, respectively. It is identified that the slow-scale instability is due to the occurrence of Hopf bifurcation, and the fast-scale instability manifests itself as period-doubling bifurcation. Furthermore, stability boundaries in various design parameter spaces considering the mismatches in different system parameters between inverter modules, as well as the effects of the current-sharing control loop on the slow- and fast-scale instabilities are also given. Besides, the influences of the nonlinear load and the control method for parallel system on the two types of instabilities are briefly discussed. These findings can be used to guide the tuning of the paralleled inverter system parameters to ensure stable operation in practice. Finally, experimental results are presented to verify the results of the simulation and theoretical analysis.

A Step Up/Down Power-Factor-Correction Converter with Modified Dual Loop Control

A step up/down AC/DC converter with modified dual loop control is proposed. The step up/down AC/DC converter features the bridgeless characteristic which can reduce bridge-diode conduction losses. Based on the step up/down AC/DC converter, a modified dual loop control scheme is proposed to achieve input current shaping and output voltage regulation. Fewer components are needed compared with the traditional bridge and bridgeless step up/down AC/DC converters. In addition, the intermediate capacitor voltage stress can be reduced. Furthermore, the top and bottom switches still have zero-voltage turn-on function during the negative and positive half-line cycle, respectively. Hence, the thermal stresses can also be reduced and balanced. Simulation and experimental results are provided to verify the validity of the proposed step up/down AC/DC converter and its control scheme.

Analysis and Modeling of Conducted EMI from an AC–DC Power Supply in LED TV up to 1 MHz

Critical conduction mode (CRM) boost power factor correction (PFC) converter is widely used in ac–dc power supplies to achieve high power factor. The switching frequency varies in a half-line cycle. In this article, both the differential-mode (DM) and common-mode (CM) electromagnetic interference (EMI) noises below 1 MHz from the ac–dc power supply in a LED TV are analyzed and modeled. The power supply consists of two parts: CRM boost PFC converter and LLC resonant converter. The conducted EMI noise and noise source voltages are measured in the time domain and then converted to the frequency domain via short-time fast Fourier transform (STFFT). Through the joint time-frequency analysis using STFFT, the drain-to-source voltage of the power MOSFET in the PFC converter is identified as the dominant noise source of both CM and DM EMI noises below 1 MHz from the power supply. The EMI current path is different during different periods of a cycle of the line voltage. During most time of a cycle, two diodes of the bridge rectifier are forward biased, and the bridge rectifier can be treated as short circuit. The current paths of DM and CM EMI noises are explained and modeled by a linear equivalent circuit model. Three parasitic capacitances need to be considered to model the CM EMI noise in this device under test. From the circuit model, transfer functions relating DM and CM EMI spectra to noise source voltage spectrum are obtained. The conducted EMI spectra are predicted by multiplying the spectrum of noise source voltage by the transfer functions. The prediction matches with measurement. The effects of parasitic capacitances on CM EMI noise are analyzed by simulation and then validated by measurement. The analysis results can help with EMI design to reduce the CM EMI.

An Improved Digital Algorithm for Boost PFC Converter Operating in Mixed Conduction Mode

This article proposes an improved digital algorithm based on predictive control for the operation of a boost power factor correction (PFC) converter in the mixed conduction mode (MCM). The proposed MCM algorithm comprises of a proposed digital conduction mode detection method, a proposed predictive discontinuous conduction mode (DCM) average current controller, a proposed digital compensation technique in DCM to account for the initial nonzero inductor current during switch turn-on and also a predictive continuous conduction mode (CCM) average current controller. The proposed algorithm flow is computationally efficient with no additional sensor/circuit requirements and ensures low harmonic content in the input current. The proposed MCM algorithm is verified experimentally on a 300-W boost PFC converter hardware prototype for converter operation in MCM, pure DCM, and pure CCM within a half line cycle. The proposed MCM algorithm is evaluated experimentally in terms of current tracking, current harmonics, and computation times.

Flicker-Free Single Switch Multi-String LED Driver With High Power Factor and Current Balancing

A flicker-free single switch multi-string LED driver with high power factor and current balancing is proposed and analyzed. It combines a pre-stage boost PFC converter and multiple second-stage buck dc-dc converters by a single active switch and multiple dc-link capacitors. With the proposed circuit configuration of multiple dc-link capacitors, the output current of each LED string can be balanced. Therefore, by controlling the output current of one LED string, the output currents of other LED strings can be controlled via current balancing of dc-link capacitors. The effect of the ripple of dc-link voltage on each output can be eliminated by fast voltage mode control loop. Therefore, flicker-free low ripple current for each LED string is achieved. With small voltage ripple across dc-link capacitors, the turn on time of active switch is almost constant in a half line cycle. Therefore, power factor correction can be achieved with inductor current of pre-stage operating in discontinuous conduction mode (DCM). Finally, prototypes of dual-string LED driver with 90-135 Vac input and 175-265 Vac input for 47 W output power are built to verify the studied results.

Effects of Junction Capacitances and Commutation Loops Associated With Line-Frequency Devices in Three-Level AC/DC Converters

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 $V_{{\text{ac}}}{\text{/650}}$ V dc/1.5-kW/450-kHz Vienna-type rectifier and a SiC mosfet based 1-kV/10-kW/280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions.

Single-Stage LED Driver Achieves Electrolytic Capacitor-Less and Flicker-Free Operation With Unidirectional Current Compensator

AC-connected light emitting diode (LED) drivers experience imbalanced energy between input and output in a half-line cycle. To achieve the flicker-free operation, the imbalanced energy needs to be buffered, often by energy-dense electrolytic capacitors. However, electrolytic capacitors are also well-known for their short lifespan. These capacitors are the limiting factor of an LED drivers’ lifespan. High voltage film capacitors and a buck converter have been used in the proposed LED driver to buffer the imbalanced energy. When P in > P LED, the extra energy is transferred from the ac input directly to the high voltage film capacitors. When P in P LED, the energy is transferred from the high voltage film capacitors to the output by the buck converter. The imbalanced energy goes through two power conversion steps in the proposed LED driver, which is one time less than other comparable electrolytic capacitor-less designs, enabling a higher efficiency to be achieved. A 28 W flyback topology based experimental prototype had been built and tested to verify the proposed design.

Two-Phase Interleaved Boost PFC Converter With Coupled Inductor Under Single-Phase Operation

When the interleaved boost power-factor correction (PFC) converter operates in a light load (<15% of nominal load), the phase-shedding control is commonly used to increase the converter's efficiency. If the inductors are coupled for high power density applications, because of the strong mutual effects of the coupled inductor, the switching of the operation phase may lead to a current flowing in the non-operation phase. In this paper, a two-phase interleaved boost PFC converter with a coupled inductor in the single-phase operation was analyzed. The operation modes of the converter in a switching cycle and a half line cycle were presented, and the modes’ variation with the load changes, as well as the power distribution, was provided. A 1-kW prototype was built to verify the analysis, and it was shown that the non-operation phase also delivers some power, which may worsen the converter's efficiency and distort the average input current waveform.

Optimum Boundary Inductance Control Concerning Limited PF for a DCM Boost PFC Converter

The discontinuous conduction mode boost power factor correction converter features zero-current turn- on for the switch, no reverse recovery in diode, and constant frequency operation. With traditional constant duty ratio control, the power transfer in each switching cycle exhibits great difference during a half-line cycle. Consequently, the peak and root mean square values of the inductor current are large, the same goes for the switch and diode. This increases not only the current stress of the power components but also the conduction and switching turn- off loss, and lowers the efficiency of the converter. Introducing third and fifth harmonics into the input current and varying the duty cycle correspondingly can reduce the aforementioned power transfer difference, and provide huge space for the increment of boundary inductance as well. An optimum boundary inductance control concerning limited power factor (PF) is proposed in this paper. For the maximum boundary inductance of the converter within wide input voltage range, the optimum harmonics amounts are analyzed and figured out. The proposed method brings about efficiency improvement, output voltage ripple reduction, and PF increase as well, especially at high input voltages. A prototype has been built and the experimental results are presented to show the validity of the scheme.