Growth Rate Of Epitaxial Layers Research Articles

Investigation on Step-Bunched Homoepitaxial Layers Grown on On-Axis 4H-SiC Substrates via Molten KOH Etching

Wafer-scale on-axis 4H-SiC epitaxial layers with very low roughness were obtained in this study. By performing carbon-rich hydrogen etching and epitaxial growth of the epitaxial layer at different temperatures, local mirror regions (LMRs) with root mean square (RMS) roughness less than 0.2 nm were obtained on the epitaxial layer surface. The LMRs’ length is tens of millimeters, and the width is sub-millimeters. The step-flow growth induced by threading screw dislocations (TSDs) was observed on the epitaxial layer surface by atomic force microscopy (AFM), together with the double bi-atomic step-flow growth induced by the step bunch, which was the cause of LMRs. Furthermore, the growth mechanism was investigated by wet etching. The etching pits were found to be associated with 3C-SiC and their effect on the growth rate of epitaxial layers was further explored.

Surface kinetics study of metal-organic vapor phase epitaxy of GaAs1−yBiy on offcut and mesa-patterned GaAs substrates

The influence of the surface step termination on the metal-organic vapor phase epitaxy of GaAs1−yBiy was explored by examining the epitaxial layer growth rate, composition, and morphology characteristics on the offcut and mesa-patterned (001) GaAs substrates. Vicinal surfaces offcut to (111)B with a high density of As-terminated steps (‘B-steps’) increased the GaAs1−yBiy layer growth rate as well as possessed the fastest lateral growth rate on mesa-patterned substrates at a growth temperature of 420°C, indicating that B-steps enhanced the Ga incorporation. With Bi accumulation on the surface, the Ga incorporation rate was reduced by the Bi preferential presence at B-steps blocking the Ga incorporation. Vicinal surfaces offcut to (111)A, which generated Ga-terminated steps (‘A-steps’) enhanced the Bi incorporation rate during growth at 380°C. This work reveals that the surface step termination plays an important role in the growth of the metastable alloy. Appropriate choices of both the substrate surface-step structure and other growth parameters could lead to an enhanced Bi incorporation.

Influence of substrate conductivity on layer thickness in LPE GaAs

Differences have been found on the growth rate of epitaxial layers grown simultaneously on semi-insulating and P and N type (1 0 0) GaAs substrates from the same Ga–As liquid solution. The layers were grown by LPE at 786°C using an initial supercooling of 15°C and a cooling rate of 0.5°C/min. The thickness of the grown layers was measured, under an optical microscope, in cleaved cross-sections etched in a FeCl 3–HCl solution. To fit the thickness-growth time data to the theoretical expression used for diffusion-limited growth it is necessary to use different initial supercoolings for the layers grown in each substrate, in spite that those layers were grown at the same time, from the same solution and therefore under exactly the same conditions.

A Simple Model for Calculating the Growth Rate of Epitaxial Layers of Silicon Carbide in Vacuum

The temperature dependence of the growth rate of epitaxial layers of silicon carbide in vacuum was calculated within the simple model based on the Hertz-Knudsen equation, taking into account the temperature-dependent sticking coefficient. The calculation results fit the experimental data well. © 2004 MAIK "Nauka/Interperiodica".

Predicting Growth Rates of SiC Epitaxial Layers Grown by Hot-Wall Chemical Vapor Deposition

The growth of device quality epitaxial layers requires precise control of the thickness and doping uniformity. By using simulations a better understanding of the growth process can be achieved and process optimization may be possible. The present work uses an extensive chemistry model, to accurately predict growth rates of epitaxial layers grown by chemical vapor deposition. Simulations are made in three dimensions to accurately model the horizontal reactor used in the experiments. Experimental results show four main growth zones, which are characterized by different morphological defects. Certain defects can be attributed to either silicon rich or carbon rich deposition, which is confirmed by X-ray photospectroscopy measurements. Different cases are studied, changing the total pressure in the growth chamber.

Si Nanowires Grown via the Vapour–Liquid–Solid Reaction

Si nanowires as thin as 10 nm have been grown using silane gas as the source gas in the Vapour–Liquid–Solid (VLS) reaction. This paper describes the nucleation, growth and oxidation of the wires and a technique developed to control the wire diameter and position. A very thin layer of Au is deposited onto a Si(111) surface at room temperature. Silane gas is then introduced into the chamber as the VLS Si source gas and the temperature is raised to 300 to 700 °C. Initially a catalytically active Au surface phase which coats the surface leads to the growth of a defective epitaxial Si layer. As Au/Si molten alloy balls nucleate and grow in size to approach the threshold size for VLS wire growth, which is determined by the Gibbs-Thomson effect, the epitaxial layer growth rate decreases and a transition to Si nanowire growth occurs. The morphology and width of the wires is strongly dependent on the growth temperature and pressure. At low pressure and high temperature relatively thick well-formed wires grow straight up from the substrate surface along the [111] direction. As the temperature is decreased and the pressure is increased thinner wires grow which tend to exhibit growth defects. The Si nanowires can be thinned down by oxidation. A light oxidation yields Si cores which are of the order of 5 nm in diameter. A method to control the position of the Si wires which exploits the difference in Au sticking coefficient on Si and SiO2 surfaces at elevated temperature (T > 540 °C) has recently been developed. Using thermally oxidized Si(111) as a starting substrate, circular holes ≈1.5 μm in diameter were etched through the SiO2 to expose the Si. The sample was heated to 700 °C and exposed to a flux of Au atoms. For low Au fluxes (≈1×1014 atoms cm—2 s—1) the Au sticking coefficient on the SiO2 surface is negligible at 700 °C but remains unity on the exposed Si surface in the holes. The liquid alloy which forms in the holes during Au deposition is able to agglomerate to form a single ball in each hole. The quantity of Au which contributes to each ball can be controlled because it is determined by the hole size and the total Au dose. When silane gas is then introduced into the chamber each alloy ball grows to form a Si wire of controlled diameter whose position is quasi-controlled by the initial patterning. No wire growth occurs on the SiO2 surface due to the absence of Au. This ability to control the size and position of the Si wires should make it possible to conduct optical and transport measurements on a single wire of known dimensions.

The Characteristics and Oxidation of Vapor - Liquid - Solid Grown Si Nanowires

AbstractThe Vapor - Liquid - Solid (VLS ) technique allows the growth of high aspect ratio Si wires. The Si nanowires formed by this technique can be thinned down by oxidation. This approach allows the formation of very thin Si cores which may be used to research the properties of Si nanostructures. In this work the growth and oxidation of these wires is characterized.In the growth a very thin layer of Au is deposited on a Si (111) surface, silane gas is introduced into the chamber as the Si source gas and the temperature is raised to 300 – 600°C. Initially a catalytically active Au surface phase leads to the growth of a defective epitaxial Si layer. As Au / Si molten alloy balls nucleate and grow in size to approach the threshold size for VLS wire growth, which is determined by the Gibbs - Thomson effect, the epitaxial layer growth rate decreases and a transition to Si nanowire growth occurs. The morphology and width of the wires is strongly dependent on the growth temperature and pressure. At low pressure and high temperature relatively thick well-formed wires grow straight up from the substrate surface along the [111] direction. As the temperature is decreased and the pressure is increased thinner wires (as thin as 10 nm ) grow which tend to exhibit growth defects. A light oxidation yields Si cores which are of the order of 5 nm in diameter.

Suppression of Arsenic Autodoping with Rapid Thermal Epitaxy for Low Power Bipolar Complementary Metal Oxide Semiconductor

Scaled bipolar transistors for bipolar complementary metal oxide semiconductor (BiCMOS) integrated circuits require low collector‐substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector‐substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic‐buried layer implant dose, and pre‐epitaxial bake temperature on autodoping using rapid thermal epitaxy (RTE). To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e., low growth rates trap less arsenic at the substrate/epi layer interface) for all growth rates studied. Next, by adjusting the prebake temperature over a range from 800 to 1050°C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950°C, at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature prebake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic‐doped buried layers for low power BiCMOS are possible.

Rapid Thermal Epitaxy for Device Applications

AbstractRapid thermal epitaxy (RTE) is studied for a variety of applications including transistors as well as optoelectronic devices. Two transistor applications are discussed here. First, the growth of n-type epitaxial layers over n+ buried layers for low power BiCMOS, and second, the growth and fabrication of charge injection transistors (CHINTs) from a multi-layer structure including strained Si1−xGex layers.Scaled bipolar transistors for BiCMOS integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic buried layer implant dose, and pre-epitaxial bake temperature on autodoping using RTE. To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e. low growth rates trap less arsenic at the substrate/epi layer interface). Next, by adjusting the pre-bake temperature over a range from 800 to 1050°C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950°C at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature pre-bake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic doped buried layers for low power BiCMOS are possible.Charge injection transistors and logic elements have been successfully implemented in a Si/Si0.7Ge0.3 heterostructure grown by RTE on a Si substrate. Shallow p+ source and drain ohmic contacts are obtained by a boron diffusion from a selectively deposited boron doped Ge layer. Room temperature operation of the charge injection transistor is demonstrated for the first time. High frequency measurements indicate a short circuit current gain cutoff frequency of 6 GHz.

Flow-graph model of epitaxial growth of A IIIB V compounds from the vapour phase

A flow-graph method was applied to model the vapour phase epitaxial growth of AB and AB 1- x C x layers. Theoretical formulas were developed giving the dependence of the epitaxial layer growth rate on the process technological parameters and showing good quality agreement with the experimental data.

Epitaxial growth of silicon carbide layers by sublimation „sandwich method”︁ (I) growth kinetics in vacuum

AbstractThe growth kinetics of SiC epitaxial layers has been investigated by sublimation sandwich‐method in vacuum at temperature range from 1600 to 2100°C. The limiting stages of the crystallization process have been determined. Silicon deficit in the growth cell was shown to result in the great retarding of SiC epitaxial layers growth due to the decreasing of evaporation coefficient by a factor of 101–102 and more. The impurities introduced into the system at low supersaturations and temperatures, especially rare‐earth elements, Al, B, Cr reduce as a rule evaporation and condensation coefficients and therefore the growth rate of epitaxial layers.

New Methods of Vapour Phase Epitaxial Growth of GaAs

New vapour growth methods using the Ga–AsCl3–H2 and GaAs–AsCl3–H2 systems are proposed. In these methods, the apparatus is basically the same as the conventional Ga–AsCl3–H2 system, but the source and the substrate are kept at the same temperature. The growth in the Ga–AsCl3–H2 system is based on the reaction between gallium monochloride and arsenic that is being passed over metallic gallium at low temperatures (<800°C). The influences of the temperature, the hydrogen flow rate, and the gas composition on the growth rate are studied. The growth in the GaAs–AsCl3–H2 system is based on the reaction of GaAs with AsCl3 at low temperatures (<700°C). The transport rate of the source GaAs and the growth rate of epitaxial layers are discussed as functions of the reaction temperature, the hydrogen flow rate, the gas composition and the position of substrate. The reaction mechanisms for the two systems are also discussed.

Growth kinetics of epitaxial layers of gallium phosphide by temperature-gradient zone recrystallization

A study is made of the dependence of the growth rate of epitaxial layers of gallium phosphide under conditions of temperature-gradient zone recrystallizatton on the thickness of the zone and the temperature. The coefficient of diffusion of phosphorus into gallium is calculated, and also the rate of change of the phosphorus concentration in the zone due to vaporization, the activation energies of the diffusion and vaporization processes, and also the atomickinetic coefficients of the crystallization process.

Une nouvelle méthode d'épitaxie en phase vapeur d'arseniure de gallium de haute pureté

High purity gallium arsenide can be prepared by vapour phase epitaxy in many ways, two of which are now well known and widely used, that is, the AsCl3/Ga/H2 system and the AsH3/Ga/HCl system. This paper describes a new vapour phase epitaxial process which uses the advantageous features of these two systems in order to give good control of stoichiometry and purity. In this proces, gallium is transported by HCl, through the monochloride GaCl, and As4 is simply evaporated from a solid deposit; the originality of the system lies in the fact that both HCl and As4 come from the reduction of AsCl3, by pure hydrogen. The results of measurements on the growth rates of epitaxial layers versus PAs4o and PGaClo are given together with the results and a discussion of the influence of the As/Ga ratio on the free carrier concentration and mobility found in epitaxial layers.

Thermodynamic Study of the Transport and Epitaxial Growth of GaAs in an Open Tube

A theory based on a thermodynamic analysis is developed and compared with experimental results obtained for transport and epitaxial growth of GaAs in GaAs-AsCl3-H2 system. The transport rate of source GaAs and the growth rate of epitaxial layers are discussed as a function of the hydrogen flow rate, the source and substrate temperatures, the mole ratio of Cl2/H2, the reaction time and the substrate orientation. A reasonable agreement is found between the theory and experimental results except the effect of the substrate orientation on growth rate.