Greater Processing Capabilities Research Articles

Interoperability Middleware for IIoT Gateways based on Standard Ontologies and AAS

Recent advancements in microelectronics, information technology, and communication protocols have led to smaller devices with greater processing capabilities and lower energy consumption. These developments have contributed to the growing number of physical devices used in industrial environments that are interconnected and communicate through the internet, allowing for the realization of Industry 4.0 and the Industrial Internet of Things (IIoT). Numerous companies are involved in producing these devices, each using different communication protocols, data structures, and IoT platforms. This has resulted in interoperability issues that need to be addressed. To mitigate these issues, this paper proposes an interoperability middleware for IIoT gateways that adopts ontologies based on international standards (IEEE 1872-2015) and the asset administration shell (AAS) using industrial frameworks.

Link State Routing Based on Compressed Sensing

In table routing protocols such as link state routing, every node in the network periodically broadcasts its link state and the state of its neighbors. These routing updates result in the transmission of a large number of packets. Some of these packets contain correlated or even redundant data which could be compressed if there is central management in the network. However, in autonomous networks, each node acts as a router, in which case central coordination is not possible. In this paper, compressed sensing is used to reduce routing traffic overhead. This can be done at nodes which have greater processing capabilities and no power consumption limitations such as backbone nodes in wireless mesh networks. A method is proposed to select a subset of nodes and thus a subset of links to probe their state. The sensed states are encoded to generate a low dimension sampled vector. This compressed link state vector is broadcast to the entire network. Nodes can then reconstruct link states from this vector using side information. Performance results are presented which demonstrate accurate anomaly detection while adapting to topology changes. Further, it is shown that a proper choice of weighting coefficients in the sampling process can improve detection performance.

Design and Verification of a Scalable Enhanced High Performance DMA Architecture for Complex SoC

As the demand of higher image quality and greater processing capabilities are growing, obtaining higher data bandwidth for on-chip processing is becoming a more and more important issue. DMA (Direct Memory Access) component, as the key element in stream processing SoC (System on Chip) [1], should be deeply researched and designed to satisfy the high data bandwidth requirement of processing units. In this paper, we introduce a scalable high-performance DMA architecture for complex SoC to satisfy rigorous high sustained bandwidth and versatile functionality requirements. Several techniques and structures are proposed in this paper. A state-in-art verification environment is built for our design to fully verify its functionality. At the end of the paper, the tape-out results are provided. The whole implementation has been silicon proven to be functional and efficient.