Graphics Processing Units Devices Research Articles

Efficient computation of the geopotential gradient in graphic processing units

Efficient computation of the geopotential gradient is essential for numerical propagators, particularly in scenarios involving low Earth orbits. Conventional geopotential calculations are based on spherical harmonics series, which become computationally demanding as the degree/order increases. This computational burden can be mitigated by means of parallelized algorithms. Additionally, certain situations lend themselves to high parallelization, such as the propagation of space debris catalogs, satellite mega-constellations, or the dispersion of particles resulting from a space collision event. This paper introduces an optimized Graphics Processing Unit (GPU) implementation designed to facilitate extensive parallelization in the geopotential gradient calculation. The formulation developed in this study is not specific to any GPU. However, to illustrate the low-level optimizations necessary for an efficient implementation, we selected the Compute Unified Device Architecture (CUDA) as the dominant and de facto standard in parallel computing. Nevertheless, most of the concepts and optimizations presented in this paper are also valid for other GPU architectures. Built upon the spherical harmonic expansion using the Cunningham formulation, which is well-suited for GPU computations, our implementation offers several variants with different tradeoffs between speed and accuracy. Besides GPU double precision, we introduced a mixed precision arithmetic –a hybrid between single and double precision– that exploits GPU capabilities with a low penalty in accuracy. The proposed algorithm was implemented as a software reusable module, and its performance was evaluated against GMAT, GODOT, and Orekit astrodynamic codes. The algorithm’s accuracy in double precision is comparable to such codes. The mixed precision version showed enough accuracy for LEO satellite propagation, with around 1 m difference in four days. Testing across different CUDA architectures revealed very high speed-up factors compared to a single CPU, reaching a speed-up of 645 for the mixed precision variant and 450 for the double precision one in the propagation of about 3200 objects with a geopotential of degree/order 126 × 126 using an A100 GPU device.

Hand-held GPU accelerated device for multiclass classification of X-ray images using CNN model

Chest X-ray (CXR) images are the primary investigation aid for many lung diseases and their follow-ups. For diagnosis of SARS-CoV-2, RT–PCR test and chest Computed Tomography (CT) are commonly used but both face false negatives for ruling out the infection. So, there is a demanding need for developing a system combined with Artificial Intelligence (AI) and CXR imaging to detect COVID-19 patients to avoid its spread. Here, a robust and efficient handheld device is proposed. It uses the computational power of the Graphics Processing Unit (GPU) and pre-trained deep learning models for analyzing the CXR images. A Resnet-50 CNN model is deployed on an NVIDIA Jetson Nano GPU module for the real-time classification of COVID-19, Tuberculosis, and Normal using CXR images. The device can perform real-time classification of CXR images from a portable X-ray machine and classify the image into one of the above categories. For the extensive training, a database of 680 COVID-19, 1230 Tuberculosis, and 1050 normal CXR images are extracted by combining several global databases like Kaggle, SIRM, RSNA, and Radiopaedia. The classification accuracy, precision, and loss rate were 0.9879, 0.9758, and 0.0196 respectively and our model would improve with larger data sets. The highly accurate and high-performance GPU device significantly plays a far-reaching role in COVID-19 diagnosis using Chest X-ray, which could be beneficial to triage the health system and to combat the outbreak of COVID-19.

Time Predictable Modeling Method for GPU Architecture with SIMT and Cache Miss Awareness

Graphics Processing Units (GPUs) are used to accelerate computing-intensive tasks, such as neural networks,data analysis, high-performance computing, etc. In the past decade or so, researchers have done a lot of work on GPU architecture and proposed a variety of theories and methods to study the microarchitectural characteristics of various GPUs. In this study, the GPU serves as a co-processor and works together with the CPU in an embedded real-time system to handle computationally intensive tasks. It models the architecture of the GPU and further considers it based on some excellent work. The SIMT mechanism and Cache-miss situation provide a more detailed analysis of the GPU architecture. In order to verify the GPU architecture model proposed in this article, 10 GPU kernel_task and an Nvidia GPU device were used to perform experiments. The experimental results showed that the minimum error between the kernel task execution time predicted by the GPU architecture model proposed in this article and the actual measured kernel task execution time was 3.80%, and the maximum error was 8.30%.

NERONE: The Fast Way to Efficiently Execute Your Deep Learning Algorithm at the Edge.

Semantic segmentation and classification are pivotal in many clinical applications, such as radiation dose quantification and surgery planning. While manually labeling images is highly time-consuming, the advent of Deep Learning (DL) has introduced a valuable alternative. Nowadays, DL models inference is run on Graphics Processing Units (GPUs), which are power-hungry devices, and, therefore, are not the most suited solution in constrained environments where Field Programmable Gate Arrays (FPGAs) become an appealing alternative given their remarkable performance per watt ratio. Unfortunately, FPGAs are hard to use for non-experts, and the creation of tools to open their employment to the computer vision community is still limited. For these reasons, we propose NERONE, which allows end users to seamlessly benefit from FPGA acceleration and energy efficiency without modifying their DL development flows. To prove the capability of NERONE to cover different network architectures, we have developed four models, one for each of the chosen datasets (three for segmentation and one for classification), and we deployed them, thanks to NERONE, on three different embedded FPGA-powered boards achieving top average energy efficiency improvements of 3.4× and 1.9× against a mobile and a datacenter GPU devices, respectively.

The implementation of the three-dimensional unified gas-kinetic wave-particle method on multiple graphics processing units

To further improve the efficiency of the unified gas-kinetic wave-particle (UGKWP) method in hypersonic rarefied non-equilibrium flows, particularly the particle simulation process, we presented the first application of the three-dimensional UGKWP method to multiple graphics processing unit (GPU) devices in this study. The wave and particle evolution components of the method are addressed using cell and particle paralleling strategies, respectively, enabling the primary loop of the GPU-based UPKWP (GPU-UGKWP) to be executed entirely by the compute unified device architecture threads on GPU devices. Concurrently, communication issues between central processing unit (CPU) nodes are resolved by employing the message passing interface model. Additionally, we introduce a tailored memory management scheme for the GPU-UGKWP method, facilitating efficient access to the particle array. Performance comparisons reveal that, relative to a single Intel Xeon Gold 6148 CPU core, the Nvidia Tesla P100 achieves a total speedup of 34 using one GPU device, and 226 with eight GPU devices, and a single Nvidia Titan V GPU device attains a speedup of 62. The speedup outcomes on multiple CPU cores and GPU devices demonstrate that the GPU-based algorithm is better suited for computationally demanding tasks, particularly in particle-dominated simulations. As evidenced by the reduced calculation time for a hypersonic technology vehicle simulation performed on the P100 cluster, GPU devices significantly outperform their CPU counterparts.

An ST 2110 Network-Attached Display Adapter for Virtualizing Production

Graphics processing unit (GPU) installations in post-production and broadcast facilities require video to be sent remotely conforming to the SMPTE ST 2110 standards for plug-and-play device connectivity. Furthermore, in such facilities, workstations are now being virtualized and hosted in the data center with what would have previously been a physically attached serial digital video (SDI) reference display replaced by an Internet Protocol (IP) network connection. We present a SMPTE ST 2110 virtual network-attached reference display adapter using commercial off-the-shelf (COTS) hardware that presents the GPU and network interface card (NIC) as a display on the computer workstation desktop. Color-accurate rendered video frames are transmitted directly from GPU device memory. Alignment of the GPU display of the rendered frame and the synchronization of the audio, video, and ancillary data streams are maintained by precision time protocol (PTP). Advanced Media Workflow Association Networked Media Open Specifications (AMWA NMOS) integration permits the discovery and registration of the virtual network-attached reference display adapter as a source node on the media network such that it can be remotely managed and controlled by software greatly simplifying the administration compared with a physically connected display and associated cables. Content creation applications send ST 2110-compliant video, audio, and ancillary data flows on the media network from a virtualized computer workstation desktop without the cost of directly integrating ST 2110 transmission capabilities.

An ultra-fast deep-learning-based dose engine for prostate VMAT via knowledge distillation framework with limited patient data

Objective. Deep-learning (DL)-based dose engines have been developed to alleviate the intrinsic compromise between the calculation accuracy and efficiency of the traditional dose calculation algorithms. However, current DL-based engines typically possess high computational complexity and require powerful computing devices. Therefore, to mitigate their computational burdens and broaden their applicability to a clinical setting where resource-limited devices are available, we proposed a compact dose engine via knowledge distillation (KD) framework that offers an ultra-fast calculation speed with high accuracy for prostate Volumetric Modulated Arc Therapy (VMAT). Approach. The KD framework contains two sub-models: a large pre-trained teacher and a small to-be-trained student. The student receives knowledge transferred from the teacher for better generalization. The trained student serves as the final engine for dose calculation. The model input is patient computed tomography and VMAT dose in water, and the output is DL-calculated patient dose. The ground-truth \\dose was computed by the Monte Carlo module of the Monaco treatment planning system. Twenty and ten prostate cases were included for model training and assessment, respectively. The model’s performance (teacher/student/student-only) was evaluated by Gamma analysis and inference efficiency. Main results. The dosimetric comparisons (input/DL-calculated/ground-truth doses) suggest that the proposed engine can effectively convert low-accuracy doses in water to high-accuracy patient doses. The Gamma passing rate (2%/2 mm, 10% threshold) between the DL-calculated and ground-truth doses was 98.64 ± 0.62% (teacher), 98.13 ± 0.76% (student), and 96.95 ± 1.02% (student-only). The inference time was 16 milliseconds (teacher) and 11 milliseconds (student/student-only) using a graphics processing unit device, while it was 936 milliseconds (teacher) and 374 milliseconds (student/student-only) using a central processing unit device. Significance. With the KD framework, a compact dose engine can achieve comparable accuracy to that of a larger one. Its compact size reduces the computational burdens and computing device requirements, and thus such an engine can be more clinically applicable.

GPU Devices for Safety-Critical Systems: A Survey

Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as autonomous driving systems. However, the integration of complex, parallel, and computationally demanding software functions with different safety-criticality levels on GPU devices with shared hardware resources contributes to several safety certification challenges. This survey categorizes and provides an overview of research contributions that address GPU devices’ random hardware failures, systematic failures, and independence of execution.

Lightweight Monocular Depth Estimation on Edge Devices

Given monocular images as inputs, monocular depth estimation (MDE) infers pixel-level depth. MDE is always a critical stage in scene sensing on edge devices. Existing MDE studies frequently employ deep neural networks (DNNs) for MDE, but they still face some problems, such as sacrificing computational complexity and efficiency in return for great precision, or losing more precision in exchange for increased efficiency. To alleviate these issues; 1) we propose an encoder–decoder network (EdgeNet) for precise and fast MDE on different edge devices. When recovering depth in the decoder, we design upsampling modules to aggregate global depth information with low computational complexity, improving the accuracy of the decoder by extracting its different ranges of depth information; 2) we develop a two-stage channel pruning method to, respectively, prune the encoder and decoder based on their characteristics. Our pruning method further reduces latency and model/computational complexity of EdgeNet, while losing little accuracy; and 3) we optimize the pruned EdgeNet to decrease graphics processing unit (GPU) scheduling overhead. The optimization accelerates MDE inference by an order of magnitude on the TX2 GPU device, when the input resolution is 224 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 224. Extensive experiments show that our strategies are effective on different edge GPU devices, when input resolutions differ in outdoor or indoor scenes. For example, compared with the state of the art, the optimized EdgeNet, respectively, reduces the GPU latency by 76.3% and 89.2% on Nano and TX2 GPU devices with 2.6% lower root mean square error when the input resolution is 128 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 416.

Fast 3D transient electromagnetic forward modeling using BEDS-FDTD algorithm and GPU parallelization

The time-step sizes of the conventional finite-difference time-domain (FDTD) method are severely restricted by the Courant-Friedrichs-Lewy stability condition. This may result in excessive iterations, high cost and large runtime, and increasing late-stage cumulative errors in 3D transient electromagnetic (TEM) forward modeling. At present, forward modeling speed is a major obstacle in the development of 3D TEM inversion. To address this issue, a new 3D TEM forward modeling algorithm is presented. In the new algorithm, the backward Euler (BE) scheme is used with a view toward relaxing the stability constraint. However, after using the BE approach, a huge sparse matrix needs to be inverted in each iteration. Directly solving such matrices by Gaussian elimination or an iterative method is still time-consuming and requires large amounts of computer memory. To improve computational efficiency, the direct-splitting (DS) strategy is adopted to transform the large sparse matrices into a series of small diagonally dominant tridiagonal matrices, which are easier to solve. Then, the complex-frequency-shifted perfectly matched layer boundary condition is implemented using the bilinear transform method to reduce the size of the model. To further speed up the calculation process, the codes are then programmed to run on graphics processing unit (GPU) devices. Three models are used for calculations, and the results are compared with other numerical methods to verify the accuracy of our algorithm. After that, to demonstrate the BEDS-FDTD algorithm’s ability to model complex earth structures, a model with a very complex shape is used for the calculation via the conformal mesh technique. In addition, the modeling speed is tested using different GPU devices. We find that an NVIDIA Tesla A100 is able to calculate the 50 × 50 × 50 cell model in only 8 s.

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

Graphics Processing Units (GPUs) are increasingly adopted in several domains where reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately, GPU devices have been shown to have a high error rate, while the constraints imposed by real-time safety-critical applications make traditional (and costly) replication-based hardening solutions inadequate. This work proposes an effective methodology to identify the architectural vulnerable sites in GPUs modules, i.e., the locations that, if corrupted, most affect the correct instructions execution. We first identify, through an innovative method based on Register-Transfer Level (RTL) fault injection experiments, the architectural vulnerabilities of a GPU model. Then, we mitigate the fault impact via selective hardening applied to the flip-flops that have been identified as critical. We evaluate three hardening strategies: Triple Modular Redundancy (TMR), Triple Modular Redundancy against SETs ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula> TMR), and Dual Interlocked Storage Cells (Dice flip-flops). The results gathered on a publicly available GPU Model (FlexGripPlus) considering functional units, pipeline registers, and warp scheduler controller show that our method can tolerate from 85% to 99% of faults in the pipeline registers, from 50% to 100% of faults in the functional units and up to 10% of faults in the warp scheduler, with a reduced hardware overhead (in the range of 58% to 94% when compared with traditional TMR). Finally, we adapt the methodology to perform a complementary evaluation targeting permanent faults and identify critical sites prone to propagate fault effects across the GPU. We found that a considerable percentage (65% to 98%) of flip-flops that are critical for transient faults are also critical for permanent faults.

Distributed parallel deep learning with a hybrid backpropagation-particle swarm optimization for community detection in large complex networks

In this paper, a parallel deep learning-based community detection method in large complex networks (CNs) is proposed. First, a CN partitioning method is employed to divide the CN into multiple chunks to improve the efficiency in terms of space and time complexities. Next, the method is integrated with two optimization algorithms: (1) backpropagation (BP), which optimizes deep learning locally within each local chunk of the CN; (2) particle swarm optimization (PSO), which is used to improve the BP optimization involving all CN chunks. PSO utilizes a multi-objective function to improve the effectiveness of the proposed method. In addition, a distributed environment is set up to conduct parallel optimization of the proposed method so that multi-local optimizations could be performed simultaneously. A set of 16 real-world CNs in a range from small to large size are used to verify the effectiveness and efficiency of the method in a benchmark study. The proposed method is implemented in multi-machines with central processing unit (CPU) and graphics processing unit (GPU) devices. The results reveal the effective role of the proposed deep learning with hybrid BP–PSO optimization in detecting communities in large CNs, which requires minimum execution time on both CPU and GPU devices.

EC-ECC: Accelerating Elliptic Curve Cryptography for Edge Computing on Embedded GPU TX2

Driven by artificial intelligence and computer vision industries, Graphics Processing Units (GPUs) are now rapidly achieving extraordinary computing power. In particular, the NVIDIA Tegra K1/X1/X2 embedded GPU platforms, which are also treated as edge computing devices, are now widely used in embedded environments such as mobile phones, game consoles, and vehicle-mounted systems to support high-dimension display, auto-pilot, and so on. Meanwhile, with the rise of the Internet of Things (IoT), the demand for cryptographic operations for secure communications and authentications between edge computing nodes and IoT devices is also expanding. In this contribution, instead of the conventional implementations based on FPGA, ASIC, and ARM CPUs, we provide an alternative solution for cryptographic implementation on embedded GPU devices. Targeting the new cipher suite added in TLS 1.3, we implement Edwards25519/448 and Curve25519/448 on an edge computing platform, embedded GPU NVIDIA Tegra X2, where various performance optimizations are customized for the target platform, including a novel parallel method for the register-limited embedded GPUs. With about 15 W of power consumption, it can provide 210k/31k ops/s of Curve25519/448 scalar multiplication, 834k/123k ops/s of fixed-point Edwards25519/448 scalar multiplication, and 150k/22k ops/s of unknown-point one, which are respectively the primitives and main workloads of key agreement, signature generation, and verification of the TLS 1.3 protocol. Our implementations achieve 8 to 26 times speedup of OpenSSL running in the very powerful ARM CPU of the same platform and outperform the state-of-the-art implementations in FPGA by a wide margin with better power efficiency.

Implementation and Analysis of Fractals Shapes using GPU-CUDA Model

The rapid evolution of floating-point computing capacity and memory in recent years has resulted graphics processing units (GPUs) an increasingly attractive platform to speed scientific applications and are popular rapidly due to the large amount of data that processes the data on time. Fractals have many implementations that involve faster computation and massive amounts of floating-point computation. In this paper, constructing the fractal image algorithm has been implemented both sequential and parallel versions using fractal Mandelbrot and Julia sets. CPU was used for the execution in sequential mode while GPUarray and CUDA kernel was used for the parallel mode. The evaluation of the performance of the constructed algorithms for sequential structure using CPUs (2.20 GHz and 2.60 GHz) and parallelism structure for various models of GPU (GeForce GTX 1060 and GeForce GTX 1660 Ti ) devices, calculated in terms of execution time and speedup to compare between CPU and GPU maximum ability. The results showed that the execution on GPU using GPUArray or GUDA kernel is faster than its sequential implementation using CPU. And the execution using the GUDA kernel is faster than the execution using GPUArray, and the execution time between GPU devices was different, GPU with (Ti) series execute faster than the other models.

Enabling Large-Scale Simulations of Quantum Transport with Manycore Computing

The non-equilibrium Green’s function (NEGF) is being utilized in the field of nanoscience to predict transport behaviors of electronic devices. This work explores how much performance improvement can be driven for quantum transport simulations with the aid of manycore computing, where the core numerical operation involves a recursive process of matrix multiplication. Major techniques adopted for performance enhancement are data restructuring, matrix tiling, thread scheduling, and offload computing, and we present technical details on how they are applied to optimize the performance of simulations in computing hardware, including Intel Xeon Phi Knights Landing (KNL) systems and NVIDIA general purpose graphic processing unit (GPU) devices. With a target structure of a silicon nanowire that consists of 100,000 atoms and is described with an atomistic tight-binding model, the effects of optimization techniques on the performance of simulations are rigorously tested in a KNL node equipped with two Quadro GV100 GPU devices, and we observe that computation is accelerated by a factor of up to ∼20 against the unoptimized case. The feasibility of handling large-scale workloads in a huge computing environment is also examined with nanowire simulations in a wide energy range, where good scalability is procured up to 2048 KNL nodes.

GMSR: A Multi-GPU Algorithm to Accelerate a Massive Validation of Biclusters

Nowadays, Biclustering is one of the most widely used machine learning techniques to discover local patterns in datasets from different areas such as energy consumption, marketing, social networks or bioinformatics, among them. Particularly in bioinformatics, Biclustering techniques have become extremely time-consuming, also being huge the number of results generated, due to the continuous increase in the size of the databases over the last few years. For this reason, validation techniques must be adapted to this new environment in order to help researchers focus their efforts on a specific subset of results in an efficient, fast and reliable way. The aforementioned situation may well be considered as Big Data context. In this sense, multiple machine learning techniques have been implemented by the application of Graphic Processing Units (GPU) technology and CUDA architecture to accelerate the processing of large databases. However, as far as we know, this technology has not yet been applied to any bicluster validation technique. In this work, a multi-GPU version of one of the most used bicluster validation measure, Mean Squared Residue (MSR), is presented. It takes advantage of all the hardware and memory resources offered by GPU devices. Because of to this, gMSR is able to validate a massive number of biclusters in any Biclustering-based study within a Big Data context.

Fingerprint Matching Using Bozorth3 Algorithm and Parallel Computation on NVIDIA Compute Unified Device Architecture

This paper studied fingerprint matching employing Bozorth3 Algorithm for matching fingerprint and parallel computation employing NVIDIA Compute Unified Device Architecture (NVIDIA CUDA). The objective of this study obtains the percentage and time processing of matching fingerprints. In this study, the fingerprint matching is done with parallel computing is applied to the GPU (Graphics Processing Unit). GPU device used in this study is the CUDA (Compute Unified Device Architecture), which is an Application Programming Interface (API) developed by NVIDIA. The development of applications with fingerprint matching serial computing on CPU and parallel computing on GPU can be applied to the CUDA API. The results from this study can be found in the performance process on the CPU and GPU. The results of this research are the process on CUDA execution time is better than the execution time on the CPU, the process is done at both the computation is to find a match in the fingerprint value.

Fast CNN Stereo Depth Estimation through Embedded GPU Devices.

Current CNN-based stereo depth estimation models can barely run under real-time constraints on embedded graphic processing unit (GPU) devices. Moreover, state-of-the-art evaluations usually do not consider model optimization techniques, being that it is unknown what is the current potential on embedded GPU devices. In this work, we evaluate two state-of-the-art models on three different embedded GPU devices, with and without optimization methods, presenting performance results that illustrate the actual capabilities of embedded GPU devices for stereo depth estimation. More importantly, based on our evaluation, we propose the use of a U-Net like architecture for postprocessing the cost-volume, instead of a typical sequence of 3D convolutions, drastically augmenting the runtime speed of current models. In our experiments, we achieve real-time inference speed, in the range of 5–32 ms, for 1216 × 368 input stereo images on the Jetson TX2, Jetson Xavier, and Jetson Nano embedded devices.

Efficient ResNet Model to Predict Protein-Protein Interactions With GPU Computing

Protein-protein interactions (PPI) play an important role in the cell activities of organisms. The deep research about PPI can help humans understand the mechanism of life activities and apply protein functions better. Nowadays, PPI prediction algorithms based on amino acid sequences using the recurrent neural network (RNN) can overcome the disadvantages of traditional biological experimental methods and achieve high accuracy. However, these algorithms are usually time-consuming and cannot take full advantage of graphics processing units (GPU) with efficient computation performance to accelerate PPI prediction, because the RNN model considers the time series of sequences. In this paper, we propose an efficient algorithm based on the residual network (ResNet) model to predict PPI (ResPPI). Our algorithm uses the embedding method to represent amino acid sequences, combining the advantages of powerful feature extraction capabilities of the ResNet with deep layers and GPU performance. The experimental results show that the ResPPI algorithm can ensure high accuracy and reduce training time greatly. Based on the ordinary GPU device, compared with the state-of-the-art LSTM model, the speed of the ResPPI algorithm is five times faster than that of the LSTM, whereas the ResPPI algorithm can achieve similar accuracy to the LSTM. Besides, in the case of unbalanced datasets, the ResPPI algorithm can perform better.

A Performance Model for GPU Architectures that Considers On-Chip Resources: Application to Medical Image Registration

Graphics processing units (GPUs) have become extremely important devices for accelerating computing performance in many applications. However, there have been few accurate models to estimate the performance of such applications running on modern GPUs. In this paper, we propose a performance model to estimate the execution times for massively parallel programs running on NVIDIA GPUs, one that takes on-chip resources and cost of data transfer between CPU and GPU into consideration. Four different GPUs with different architectures were used to evaluate our model. We demonstrated the effectiveness of the proposed model by applying it to various tasks in medical image registration. Experiments have demonstrated that by capturing on-chip GPU resources and data transfer time with our model, we were able to obtain a more accurate prediction of the actual running time, compared to the traditional model. Moreover, by using the optimal value of the block size parameter, estimated by our model, to accelerate the landmark tracking task on GPU devices, speedups of approximately 80×, 100×, 200× and 800×, on the C2050, K20c, M5000 and P100 can be achieved, making it possible to track massive numbers of landmarks and thereby improving the registration accuracy.