Graphene Barristor Research Articles

Graphene barristors for de novo optoelectronics.

Graphene-based vertical Schottky-barrier transistors (SBTs), renowned as graphene barristors, have emerged as a feasible candidate to fundamentally expand the horizon of conventional transistor technology. The remote tunability of graphene's electronic properties could endorse multi-stimuli responsive functionalities for a broad range of electronic and optoelectronic applications of transistors, with the capability of incorporating nanochannel architecture with dramatically reduced footprints from the vertical integrations. In this Feature Article, we provide a comprehensive overview of the progress made in the field of SBTs over the last 10 years, starting from the operating principles, materials evolution, and processing developments. Depending on the types of stimuli such as electrical, optical, and mechanical stresses, various fields of applications from conventional digital logic circuits to sensory technologies are highlighted. Finally, more advanced applications toward beyond-Moore electronics are discussed, featuring recent advancements in neuromorphic devices based on SBTs.

Dual-channel P-type ternary DNTT–graphene barristor

P-type ternary switch devices are crucial elements for the practical implementation of complementary ternary circuits. This report demonstrates a p-type ternary device showing three distinct electrical output states with controllable threshold voltage values using a dual-channel dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]-thiophene–graphene barristor structure. To obtain transfer characteristics with distinctively separated ternary states, novel structures called contact-resistive and contact-doping layers were developed. The feasibility of a complementary standard ternary inverter design around 1 V was demonstrated using the experimentally calibrated ternary device model.

Low-Power Complementary Inverter Based on Graphene/Carbon-Nanotube and Graphene/MoS2 Barristors.

The recent report of a p-type graphene(Gr)/carbon-nanotube(CNT) barristor facilitates the application of graphene barristors in the fabrication of complementary logic devices. Here, a complementary inverter is presented that combines a p-type Gr/CNT barristor with a n-type Gr/MoS2 barristor, and its characteristics are reported. A sub-nW (~0.2 nW) low-power inverter is demonstrated with a moderate gain of 2.5 at an equivalent oxide thickness (EOT) of ~15 nm. Compared to inverters based on field-effect transistors, the sub-nW power consumption was achieved at a much larger EOT, which was attributed to the excellent switching characteristics of Gr barristors.

Graphene/MoS₂ Thin Film Based Two Dimensional Barristors With Tunable Schottky Barrier for Sensing Applications

In this work, a large-area MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /graphene barristor device, with an electrically tunable Schottky barrier height, has been studied for detection of various gaseous analytes. The Schottky barrier height could be modulated by over 0.65 eV, allowing the drain current to be tuned by many orders of magnitude. Using diluted NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gases as analytes, the performance of the barristor device was compared with individual MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene based planar FETs, where the barristor device outperformed its counterparts in terms of response magnitude and limit of detection. Due to the atomically thin nature of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene, electric field applied to one material could not be fully screened from the other one, which allowed both materials to act as a composite structure when analyte molecules interacted with the barristor device. This apparently reversed the dopant behavior of NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , while increasing the device sensitivity through subthreshold operation. Both conductance and capacitance based measurements are presented to highlight the charge transfer and barrier height modulation, to support the unique sensing mechanism observed in the 2D barristor device. A lower limit of detection in low ppb is established for NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and low ppm for NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , which could be further tuned by altering gate-drain bias conditions.

Monolithic Tandem Multicolor Image Sensor Based on Electrochromic Color-Radix Demultiplexing.

Optical data acquisition has been set as one of the milestones to testify the developments aimed at harnessing the full potential of the spatial and temporal data processing capabilities of the advanced semiconductor technology. A highly promising approach to drive the level of acquisition beyond the current technological node is the vertical integration of multiple photodetectors. However, vertical integration so far requires the same level of circuit complexity as lateral integration from the incapability of monolithic integration. Here, an electrochromic device architecture is introduced that enables realization of a monolithic tandem multicolor photodetector. The device, composed of vertically stacked p-type and n-type graphene barristors, is demonstrated to be capable of regulating the balanced charge transport under any desired illumination wavelengths. It exhibits variable anti-ambipolar charge transport behavior, which yields sensitive voltage-controlled photoconductive gain spectra. These electrical behaviors are utilized to fabricate an optoelectronic logic sensor that can demultiplex the desired color coordinate or wavelength in the constituent array with high color accuracy.

Energy-efficient three-terminal SiO memristor crossbar array enabled by vertical Si/graphene heterojunction barristor

A three-terminal memristor is an electronic memory architecture that is particularly suitable for next-generation devices owing to its customizable intrinsic switching characteristics. However, its slow switching speed and lack of high-density array structure has hindered its applicability thus far. In this study, we have designed and fabricated a novel architecture by vertically integrating a silicon oxide (SiOx) memristor and a graphene barristor, which can be readily extended to a 16 × 16 crossbar array. Notably, the unipolar resistive switching of the SiOx memristor can be actively modulated by controlling a silicon (Si) phase filament via the barristor’s electrostatic gating. Such gate-tunable SiOx memristor in the array was observed to exhibit excellent electrical performance, e.g., increased switching speed (up to ~35 ns), increased switching probability, enhanced uniformity, and decreased operating voltage. The energy consumption is also significantly improved 4 nJ to 2 pJ via the gating, which exhibits lower than other three-terminal memristors. Moreover, it was able to sustain a high ON–OFF ratio (>106), multi-bit capability (~9 states), and stable endurance and retention properties regardless of gating. As an additional potential application, nonvolatile universal logic gates, including NOT, NOR, and NAND gates, were successfully implemented in this study based on simple circuits containing gate-tunable SiOx memristors. We believe that the proposed gate-tunable SiOx memristor represents a distinctive and novel development toward a fast, low energy, and extendable three-terminal memristor platform for electronic devices, thus undertaking a major step in unleashing the potential of memristors to support the growing demands of cutting-edge technologies.

Threshold Voltage Modulation of a Graphene–ZnO Barristor Using a Polymer Doping Process

AbstractA method to modulate the threshold voltage of a graphene–ZnO barristor is investigated. Two types of polymers, polyethyleneimine (as an n‐type dopant) and poly (acrylic acid) (as a p‐type dopant), are used to pre‐set the initial Fermi level of the graphene. The threshold voltage of the graphene barristor can be modulated between −2.0 V (n‐type graphene) and 1.2 V (p‐type graphene) while modulating the Fermi level of the graphene by 120 meV. This process provides a scalable and facile method to adjust the threshold voltage of graphene–semiconductor junction‐based devices, which is a crucial function required to implement graphene‐based electronic devices in integrated circuits.

Piezoelectrically modulated touch pressure sensor using a graphene barristor

A touch pressure sensor using a graphene-Si Schottky junction barristor gated with the piezoelectric polymer poly(vinylidenefluoride-co-trifluoroethylene) has been demonstrated that combines a high on–off ratio (over 102) and low leakage current characteristics. The performance of this device was optimized by presetting the initial Fermi level of graphene using a polymer doping process. Sensing current modulation ratios up to 312% were achieved under 3 MPa touch pressure.

Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

Piezotronic graphene barristor: Efficient and interactive modulation of Schottky barrier

The piezopotential generated in non-centrosymmetric crystals under external mechanical stimuli can be exploited to modulate the contact characteristics at the metal-semiconductor interface. The extent of electric modulation by the piezopotential was found to be moderate. This is mainly because the piezopotential was designed to alter the band bend of the semiconductor layer, which changed the injection barrier by 0.1 eV. We propose an efficient method to utilize the piezopotential for modulating Schottky barrier, i.e. piezotronic graphene barristor. This was done by capacitively coupling the piezoelectric material with a Schottky barrier (SB)-tunable graphene electrode, using an ion gel electrolyte. Through capacitive coupling, the piezopotential could modulate the work function of a graphene electrode by 0.89 eV. This was visualized directly using Kelvin probe force microscopy experiments for the first time. A large change in the work function of graphene allowed effective tuning of the height of the SB formed at the graphene/semiconductor junction. Consequently, a piezoelectric nanogenerator (PENG) could change the current density of the semiconductor layer by more than three orders of magnitude with strain, and yield a high current density larger than 10.5 A cm-2. Multistage modulation of the height of the SB at the junction was also successfully demonstrated by integrating two PENGs with ion gel. This work presents an efficient method for harnessing the piezopotential generated from PENG to actively control the operation of flexible electronics through external mechanical stimuli.

A graphene barristor using nitrogen profile controlled ZnO Schottky contacts.

We have successfully demonstrated a graphene-ZnO:N Schottky barristor. The barrier height between graphene and ZnO:N could be modulated by a buried gate electrode in the range of 0.5-0.73 eV, and an on-off ratio of up to 107 was achieved. By using a nitrogen-doped ZnO film as a Schottky contact material, the stability problem of previously reported graphene barristors could be greatly alleviated and a facile route to build a top-down processed graphene barristor was realized with a very low heat cycle. This device will be instrumental when implementing logic functions in systems requiring high-performance logic devices fabricated with a low temperature fabrication process such as back-end integrated logic devices or flexible devices on soft substrates.

Theoretical Analysis and Experimental Optimization of Graphene/TMD Heterojunction Barristors

Despite tremendous interest in graphene due to its superior electrical and remarkably strong mechanical properties, its semi-metallic property (zero bandgap) causing extremely low on/off-current ratio has still prevented integrating successfully graphene-based electronic applications. Although several approaches were reported to overcome this weak point, such as graphene nanoribbon, graphene nanoconstriction, graphene quantum dot, and dual-gated bilayer graphene, sufficiently high on/off-current ratio for logic applications was not demonstrated yet. Recently, in order to resolve the low on/off-current ratio, vertical graphene-based heterojunction barristors were proposed, where the drain current in the barristor devices is controlled by adjusting the barrier height between graphene and another semiconductor through gate biasing. These barristors were based on heterojunction with another class of atomically thin two-dimensional (2D) materials named transition metal dichalcogenides (TMDs) including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tin disulfide (SnS2) and tungsten disulfide (WS2), tungsten diselenide (WSe2).[1-4] Because the TMD materials have high scalability, excellent junction interface quality, and low contact resistance, the vertical graphene/TMD heterojunction barristors are expected to be used for future low-power wearable devices. However, the graphene layer on SiO2 that was normally used as a gate dielectric in the above works suffers from a charge puddle effect. Specifically, because the charge puddle phenomenon seems to degrade the performance of the graphene barristors by limiting modulation of the Fermi level of graphene, it is very important to suppress the charge puddles on graphene. In addition, most researches related with graphene/TMD heterojunction barristors remained on the level of qualitative analysis of device operations, consequently hindering further optimization and development. Here, we theoretically and experimentally investigated the influence of the graphene Fermi level position on the performance of a graphene/TMD heterojunction barristor. Then, we optimized the graphene/TMD heterojunction devices fabricated on MoS2 and WSe2 by suppressing charge puddle effect. Through a 3-aminopropyltriethoxysilane (APTES) treatment, which was applied in order to block the charge puddles on graphene, the on/off-current ratio values were improved by a factor of 32 and 230 in the graphene/MoS2 and graphene/WSe2 heterojunction barristors, respectively. Finally, based on first-principle density functional theory (DFT) calculations coupled with temperature-dependent current-voltage measurements and a theoretical analysis model, we quantitatively studied the atomistic origins of the operation mechanism in the graphene/TMD heterojunction barristors. [1] Y.-F. Lin, W. Li, S.-L. Li, Y. Xu, A. Aparecido-Ferreira, K. Komatsu, H. Sun, S. Nakaharai, K. Tsukagoshi, Nanoscale 2014, 6, 795-799. [2] W. J. Yu, Z. Li, H. Zhou, Y. Chen, Y. Wang, Y. Huang, X. Duan, Nat. Mater. 2013, 12, 246-252. [3] Y. Sata, R. Moriya, T. Yamaguchi, Y. Inoue, S. Morikawa, N. Yabuki, S. Masubuchi, T. Machida, J. J. Appl. Phys. 2015, 54, 04DJ04. [4] T. Georgiou, R. Jalil, B. D. Belle, L. Britnell, R. V. Gorbachev, S. V. Morozov, Y.-J. Kim, A. Gholinia, S. J. Haigh, O. Makarovsky, L. Eaves, L. A. Ponomarenko, A. K. Geim, K. S. Novoselov, A. Mishchenko, Nat. Nanotechnol. 2013, 8, 100-103.

Direct Determination of Field Emission across the Heterojunctions in a ZnO/Graphene Thin-Film Barristor.

Graphene barristors are a novel type of electronic switching device with excellent performance, which surpass the low on-off ratios that limit the operation of conventional graphene transistors. In barristors, a gate bias is used to vary graphene's Fermi level, which in turn controls the height and resistance of a Schottky barrier at a graphene/semiconductor heterojunction. Here we demonstrate that the switching characteristic of a thin-film ZnO/graphene device with simple geometry results from tunneling current across the Schottky barriers formed at the ZnO/graphene heterojunctions. Direct characterization of the current-voltage-temperature relationship of the heterojunctions by ac-impedance spectroscopy reveals that this relationship is controlled predominantly by field emission, unlike most graphene barristors in which thermionic emission is observed. This governing mechanism makes the device unique among graphene barristors, while also having the advantages of simple fabrication and outstanding performance.

Characterization and Physical Modeling of Turn-On Voltage, Saturation Voltage and Transition Slope in Graphene Barristors

In this paper, we present theoretical definitions and physical backgrounds of turn-on voltage, saturation voltage and transition slope in graphene-based variable-barrier transistors (barristors). We show that they are three main characteristics parameters of the device and are of the key factors in determining whether barristor is applicable for the future nanoelectronics. Furthermore, because of the importance of physical modeling of semiconductor devices, we address this issue and develop physical expressions, in closed form, for these characteristics. We also investigate the conformity of the functional dependence of our models and their results variations regarding to the device parameters with the reports of the previous works. Finally, we physically discuss how the variation of the device parameters, such as bias condition and doping density, can influence the aforesaid main characteristics of barristor.

Small-signal modeling of graphene barristors

This paper presents a small-signal model for graphene barristor, a promising device for the future nanoelectronics industry. Because of the functional similarities to the conventional FET transistors, the same configuration and parameters, as those of FETs, are assumed for the model. Transconductance, output resistance, and parasitic capacitances are the main parameters of the small signal equivalent circuit modeled in this work. Recognizing the importance of physical modeling of novel semiconductor devices, we develop physical compact expressions for the device radio-frequency characteristics. Furthermore, we clarify the physics behind the variation of the characteristics as the device parameters change. We also validate our model results with available simulation results. Impact of equilibrium Schottky barrier height of the graphene–silicon junction on the radio frequency performance of barristor is investigated, too.

Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.