Grained Reconfigurable Architectures Research Articles

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

Coarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

Survey on Multigrained Reconfigurable Architecture using Parallel Mapping Method

Objectives: In previous methodology, only ALU operations are seen with respect to the network on chip with this power and delay is high whereas in present research, Multi-grained reconfigurable architecture is used which reduces power and delay. In this method we can also perform multiple FFT, DCT, FIR and channel encoder. Methods: For execution, the number of instructions is flapped by associating pipelining technique which is splitted in stages. Every stage completes an area of parallely connected instructions at a time. A pope is created, with the interconnection of stages where instructions are fed at amend, progresses through these stages and exits at other end. The group of Function Units (FU'S) was connected in a mesh style network in CGRA'S. Here, the subsets of FU's are accessed only with help of segregation of register files through CGRA's that which carries temporary values. In general word operations like addition, subtraction and multiplication were carried out by these function units. Findings: For better execution characteristics of parallel mapping on MGRA, more PE utilisation rate and less memory access overhead are considered as resulting conditions. Lastly, Multi Grained Reconfigurable Architecture (MGRA) is the proposed research work where processing element consists of a multiple operations like FFT, DCT, FIR, Channel Encoder etc. The proposed architectures require multiple processing elements to execute parallel process as to reduce PE's complexity. A new folding tree algorithm is proposed (MGRA) with CRGA is proposed to eliminate PE's. This method reutilizes PE's to redistribute data from multiple nodes and the controller is integrated with current CGRA to scan the processing nodes with common expression executions. By using nested loop pipelining the Multi grained reconfigurable architecture comprises the advantages of low power and delay when compared to the existing architectures. Application: MGRA used in communication, digital signal processing.

데이터를 고려한 저전력 소모 CGRA 매핑 알고리즘

모바일 시장 및 소형 전자기기 시장의 발달에 따라 고성능 프로세서에 대한 요구 또한 커지게 되었다. 재구성형 프로세서(CGRA)는 고성능과 저전력 소모를 동시에 만족시키는 프로세서로 ASIC의 고성능 저전력을 대체하면서도 하드웨어를 쉽게 재디자인 할 수 있도록 구성된 프로세서이다. 어플리케이션의 구조에 따라 CGRA의 전체수행시간이 프로세서 자체의 수행시간보다 데이터의 전송시간에 종속되는 경우가 있다. 이 논문에서는 데이터 전송시간에 따라 수행에 사용되는 자원을 최적화 함으로써 전력소모를 줄이는 매핑 알고리즘을 제안하였다. 제안된 알고리즘을 사용한 경우, 기존의 방식보다 최대 73%, 평균 56.4%의 전력소모를 줄일 수 있었다. The demand of high performance processor is soaring due to the extending of mobile and small electronic device market. CGRA(Coarse Grained Reconfigurable Architecture) is the processor satisfying both of performance and low-power demands and a great alternative of ASIC that can be reconfigured. This paper presents a novel low-power mapping algorithm that optimizes the number of used computation resource in the mapping phase by considering data transfer time. Compared with previous mapping algorithm, ours reduce energy consumption by up to 73%, and 56.4% on average.