Graded-channel SOI nMOSFETs Research Articles

Study of the Drain Leakage Current Behavior in Graded-Channel SOI nMOSFETs Operating at High Temperatures

The theoretical and experimental study of drain leakage current behavior in Graded-Channel ( GC ) SOI nMOSFETs operating at high-temperatures ( up to 300oC ) is analyzed and discussed here. Through the studies it was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. Also, it was observed that the drain leakage behavior is similar to the conventional SOI nMOSFETs which effective channel length being equal in both structures when the GC SOI nMOSFETs has the same channel doping level in the higher doped region. Numerical bidimensional simulations and experimental data were used in order to compare and discuss all the results.

Analog Behavior of Submicron Graded-Channel SOI MOSFETs Varying Channel Length, Doping Concentration and Temperature

In this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductorswere used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature.

Liquid Helium Temperature Operation of Graded-Channel SOI nMOSFETs

This work reports, for the first time, the operation of Graded-Channel SOI nMOSFETs at liquid helium temperature. As expected, for all measured devices it has been observed that at 4.2K the transconductance increases with respect to room temperature as a consequence of the mobility rise. On the opposite hand, all the studied devices demonstrated a degradation of the output conductance with temperature reduction. However, this degradation is attenuated below 90K. As a consequence, an increase of the Early voltage and of the intrinsic voltage gain were obtained, in contrast to the data reported in the literature, for devices operating down to 100K. It is demonstrated that GC SOI presented larger Early voltage increase at 4.2K than at room temperature. The rise of the voltage gain promoted by GC architecture has shown to be constant with temperature down to 4.2K.

Analysis of the Low-Frequency Noise in Graded-Channel and Standard SOI nMOSFET

In this paper a comparison between the low-frequency noise in graded-channel SOI nMOSFETs (GC SOI MOSFET) and standard fully depleted (FD) SOI nMOSFETs will be presented. The evolution of noise with bias and frequency, mainly in the GC SOI MOSFETs, will be demonstrated. Numerical bidimensional simulations are used to reproduce the same tendencies observed experimentally in order to allow for a physical insight on the noise in GC SOI transistors.

Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded-Channel SOI nMOSFETs in a Wide Temperature Range

This work presents an experimental comparative analysis of the behavior of current mirrors implemented with standard uniformly doped and Graded-Channel (GC) SOI nMOSFETs as a function of the temperature. Three different current mirror architectures were used, Common-source, Wilson and Cascode. The experimental results show that the use of Graded-Channel transistors promotes not only the increase of the output swing, but also the increase of the output resistance in all evaluated architectures, in comparison to the standard uniformly doped counterpart. Despite some degradation observed with the temperature reduction, current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors.

Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded Channel SOI nMOSFETs in a Wide Temperature Range

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Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

In this work the performance of graded-channel (GC) SOI MOSFETs operating as source-follower buffers is presented. The experimental analysis is performed by comparing the gain and linearity of buffers implemented with GC and standard SOI MOS devices considering the same mask dimensions. It is shown that by using GC devices, buffer gain very close to the theoretical limit can be achieved, with improved linearity, while for standard devices the gain departs from the theoretical value depending on the inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to confirm some hypotheses proposed to explain the gain behavior observed in the experimental data. By using numerical simulations the channel length has been varied, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are adopted. It has also been shown that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with a standard SOI MOSFET, without gain loss or linearity degradation.

Channel Length Influence on the Performance of Source-Follower Buffers Implemented with Graded-Channel SOI nMOSFETs

This work presents an evaluation of the influence of channel length on the performance of graded-channel (GC) SOI nMOSFETs operating as source-follower buffers. Experimental data is used to compare the buffer gain and linearity of GC and standard SOI nMOS transistors for different mask channel lengths and similar effective channel length. Two-dimensional numerical simulations were also performed, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are used. The simulated results indicate that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with the standard counterpart, without gain degradation or linearity worsening.

The low-frequency noise behaviour of graded-channel SOI nMOSFETs

It is shown that the low-frequency noise in graded-channel (GC) SOI nMOSFETs is generally of the flicker or 1/ f noise type. The corresponding input-referred noise spectral density is markedly higher than for the conventional uniformly doped or the intrinsic un-doped fully depleted n-channel SOI transistors. However, this increase can only be partially explained by the effective channel length reduction provided by the lightly doped region of the GC structure. It is furthermore demonstrated that the underlying noise mechanism for the GC structures is rather related to carrier number fluctuations compared with mobility fluctuations for the intrinsic or the uniformly doped fully depleted device. It is concluded that for optimal analog performance of GC SOI nMOSFETs, high gain has to be traded off for higher 1/ f noise.

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS

This paper studies the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs and designed to provide high open-loop voltage gain or high gain-bandwidth characteristics. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI nMOSFETs, are performed showing that the GC OTAs presents larger open-loop voltage gain without degrading the phase margin, unit gain frequency and slew rate simultaneously with a significant required die area reduction depending on LLD/L ratio used. Circuit simulations and experimental results are used to qualify the analysis.