GPU Solution Research Articles

3D Modelling for the Hajj and Umrah Pilgrims

A 3D simulation model is generated that can be used for a virtual representation of people who are performing Hajj and Umrah so that future travelers can gather the necessary information to perform religious ceremonies and be well prepared before arrival to the holy places. Traffic and pedestrian management in the areas is also presented. The purpose is to speed up the calculation of all events of interest to the authorities in a simulator, such as the behavior of vehicles, pedestrians on the streets, and worshippers. Two GPU solution alternatives and one CPU solution alternative are proposed, and the performance of the proposed solutions is also compared.

MIMO-SA-Based 3-D Image Reconstruction of Targets Under Illumination of Terahertz Gaussian Beam—Theory and Experiment

For the 3-D terahertz (THz) holographic imaging, this work proposes an extended phase-shift migration (PSM) reconstruction algorithm based on multiple-input-multiple-output (MIMO) array with an orthogonal synthetic aperture (SA). For this MIMO-SA-based imaging mechanism, the accurate expression of the signal spatial spectrum can also be obtained by utilizing the method of stationary phase (MSP). Meanwhile, the analytical expression of the reconstructed 3-D point-spread function (PSF) for target under the illumination of MIMO-SA-based THz Gaussian beam is derived to provide the theoretical spatial resolutions quantitatively. A serial of simulation results with fairly good agreement were given to verify the accuracy of the proposed MIMO-SA-based PSM reconstruction algorithm. Meanwhile, due to the PSM’s characteristic of phase shift compensation along the range direction, the image reconstruction process can also be implemented and accelerated by a GPU solution. Finally, two types of MIMO-SA-based prototype imagers are applied for the proof-of-principle experiments. The first prototype imager is configured with one transmitter and two receivers in 0.3-THz band. The MIMO linear array including arbitrary number of transmitters/receivers can be realized by controlling their positions in a low-cost way with the help of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$x$</tex-math> </inline-formula> -axis of a 2-D scanner. The second prototype imager is configured with eight transmitters and eight receivers in 0.2-THz band. The experimental results from the two prototype imagers can validate the effectiveness on image reconstruction quality.

Distributed large-scale graph processing on FPGAs

Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators’ resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host’s file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device.

Dadu-SV: Accelerate Stereo Vision Processing on NPU

Binocular vision and neural networks (CNNs) are widely seen in modern intelligent vision processing systems, such as robotics, autonomous vehicles, and AR gadgets. However, both the classic semiglobal matching (SGM) and deep CNNs entail substantial computing resource to reach the performance goal. Traditional embedded CPU/graphic processor unit (GPU) cannot simultaneously meet the processing speed and energy requirement, while the specialized circuits dedicated to SGM and CNN processing, respectively, will take considerable hardware and development costs. However, as the popularity of deep learning, neural processing units (NPUs) become prevalent in many embedded and edge devices, which possess high throughput computing power to deal with the matrix operations involved by neural networks. In this work, we attempt to take advantage of the neural processing architectures integrated in SoC chips to accelerate the SGM process, so that the hardware resources will be better utilized instead of investing more resources to create specialized SGM components. Thereby, this letter first deploys SGM on NPU by converting the incompatible operations into the neural-computing flow, and a configurable neural processing element is proposed to flexibly support various vector operation sequences. Then, a hybrid dataflow scheduler and the corresponding hardware modification are introduced to accelerate the cost processing, improving hardware utilization and on-chip memory footprint and access. Our solution runs at 45 fps for an image size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times 480$ </tex-math></inline-formula> , with 128 disparity levels. The speed-energy efficiency is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$52\times $ </tex-math></inline-formula> better than the GPU (Jetson TX1) solution with negligible additional hardware overhead and accuracy loss.

Remarks on the numerical approximation of Dirac delta functions

We investigate the convergence rate of the solutions of one and two-dimensional Poisson-type PDEs where the Dirac delta function, representing the forcing term, is approximated by several expressions.The goal is to see if the solution to a Poisson’s equation converges when solved by a numerical method, with a source or sink approximated using a delta proposed in the literature. We will look at two parameters, how fast it converges, by estimating the order of convergence, and how well, by calculating the error between the analytical form and the numerical result. We investigate smoothed discrete delta functions based on the Immersed boundary (IB) approach, and we revisit their definitions, as in level set methods, by expanding their support for assessing higher-order of convergence in PDE solutions. We developed a Python package utilizing FiPy, a PDE solver based on the finite volume (FV) technique, and accelerated the solver with the AmgX package, a GPU solution. We have observed that when the support is wider, better results may be achieved. Moreover, the overall trends of error and the convergence rate in the 2D configuration differ from the 1D problems.

Study of the accuracy and applicability of the difference scheme for solving the diffusion-convection problem at large grid Péclet numbers

The work is devoted to the study of a difference scheme for solving the diffusion-convection problem at large grid Péclet numbers. The suspension transport problem numerical solving is carried out using the improved Upwind Leapfrog difference scheme. Its difference operator is a linear combination of the operators of Upwind and Standard Leapfrog difference schemes, while the modified scheme is obtained from schemes with optimal weighting coefficients. At certain values of the weighting coefficients, this combination leads to mutual compensation of approximation errors, and the resulting scheme gets better properties than the original schemes. In addition, it includes a cell filling function that allows simulating problems in areas with complex geometry. Computational experiments were carried out to solve the suspension transport problem, which arises, for example, during the propagation of suspended matter plumes in an aquatic environment and changes in the bottom topography due to the deposition of suspended soil particles into the sediment during soil unloading into a reservoir (dumping). The results of modeling the suspension transport problem at various values of the grid Péclet number are presented. The algorithm implementation was carried out using the software and hardware architecture of parallel computing: on a central processing unit (Central Processing Unit - CPU) and on a graphics accelerator (Graphics Processing Unit - GPU). The solution to the applied problem has shown its efficiency on the CPU with small computational grids and, if it is necessary to decrease the space steps, then the GPU solution is preferable. It was found that, when using the modified Upwind Leapfrog scheme, an increase in the speed of the water flow does not lead to a loss of solution accuracy due to dissipative sources and is accompanied by an insignificant increase in computational labor costs.

Using analysis information in the synchronization‐free GPU solution of sparse triangular systems

SummaryThe solution of sparse triangular linear systems is one of the most important building blocks for a large number of science and engineering problems. For these reasons, it has been studied steadily for several decades, principally in order to take advantage of emerging parallel platforms. In the context of massively parallel platforms such as GPUs, the standard strategy of parallel solution is based on performing a level‐set analysis of the sparse matrix, and the kernel included in the nVidia cuSparse library is the most prominent example of this approach. However, a weak spot of this implementation is the costly analysis phase and the constant synchronizations with the CPU during the solution stage. In previous work, we presented a self‐scheduled and synchronization‐free GPU algorithm that avoided the analysis phase and the synchronizations of the standard approach. Here, we extend this proposal and show how the level‐set information can be leveraged to improve its performance. In particular, we present new GPU solution routines that attack some of the weak spots of the self‐scheduled solver, such as the under‐utilization of the GPU resources in the case of highly sparse matrices. The experimental evaluation reveals a sensible runtime reduction over cuSparse and the state‐of‐the‐art synchronization‐free method.

Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA

3-D convolutional neural networks (3-D CNNs) are used efficiently in many computer vision applications. Most previous work in this area has concentrated only on design and optimization of accelerators for 2-D CNNs, with few attempts having been made to accelerate 3-D CNNs on FPGA. We find the acceleration of 3-D CNNs on FPGA to be challenging due to their high computational complexity and storage demands. More importantly, although the computational patterns of 2-D and 3-D CNNs are analogous, the conventional approaches that have been adopted for acceleration of 2-D CNNs may be unfit for 3-D CNN acceleration. In this paper, in order to accelerate 2-D and 3-D CNNs using a uniform framework, we first propose a uniform template-based architecture that uses templates based on the Winograd algorithm to ensure the rapid development of 2-D and 3-D CNN accelerators. Then, with the aim of efficiently mapping all layers of 2-D /3-D CNNs onto a pipelined accelerator, techniques are developed to improve the throughput and computational efficiency of the accelerator, including layer fusion, layer clustering, and workload-balancing scheme. Finally, we demonstrate the effectiveness of the deep pipelined architecture by accelerating real-life 2-D and 3-D CNNs on the state-of-the-art FPGA platform. On VCU118, we achieve 3.7 TOPS for VGG-16, which outperforms state-of-the-art FPGA-based CNN accelerators. Comparisons with CPU and GPU solutions demonstrate that our implementation of 3-D CNN achieves gains of up to $17.8\times $ and $64.2\times $ in performance and energy relative to a CPU solution, and a $5.0\times $ energy efficiency gain over a GPU solution.

Embedded GPU 3D Panoramic Viewing System Based on Virtual Camera Roaming 3D Environment

The traditional 2D panoramic view has the problem of small imaging range, low utilization of original image and serious stretching of the foreground. This paper designs a 3D panoramic viewing system. The real-time performance of the panoramic system requires a large number of parallel image transformations. The general-purpose processor CPU is incapable. This paper designs an embedded GPU solution. The core computing module is based on NXP's i.MX6Q application processor and builds an embedded Linux system. Using V4L2 to capture images to reduce memory and CPU usage, and use OpenGL ES shaders to process image transformations in parallel at high speed. Because it is in a 3D environment, it is impossible to cover all images through a still viewpoint like a 2D look-around. In order to roam the 3D scene, this paper proposes to design a virtual camera system. Using the virtual camera to roam the 3D environment, realize the virtual viewpoint in the 3D scene, traverse each scene in the grid, eliminate the dead angle of the field of view, and finally realize the 3D panoramic view, and verified on the embedded hardware platform, which can clearly roam every image on the surface. And recorded the video of 3-D looping. Experiments show that the 3D panoramic viewing system proposed in this paper has excellent performance and good effects. It has a good real-time performance on the image display, and the response speed is increased by 5%. The main operation is undertaken by the GPU and only takes a small number of CPU resources. The proposed virtual camera system can better realize the 3D panoramic view.

FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL

The Square Kilometre Array (SKA) project will be the world’s largest radio telescope array. With its large number of antennas, the number of signals that need to be processed is dramatic. One important element of the SKA’s Central Signal Processor package is pulsar search. This article focuses on the FPGA-based acceleration of the Frequency-Domain Acceleration Search module, which is a part of SKA pulsar search engine. In this module, the frequency-domain input signals have to be processed by 85 Finite Impulse response (FIR) filters within a short period of limitation and for thousands of input arrays. Because of the large scale of the input length and FIR filter size, even high-end FPGA devices cannot parallelise the task completely. We start by investigating both time-domain FIR filter (TDFIR) and frequency-domain FIR filter (FDFIR) to tackle this task. We applied the overlap-add algorithm to split the coefficient array of TDFIR and the overlap-save algorithm to split the input signals of FDFIR. To achieve fast prototyping design, we employed OpenCL, which is a high-level FPGA development technique. The performance and power consumption are evaluated using multiple FPGA devices simultaneously and compared with GPU results, which is achieved by porting FPGA-based OpenCL kernels. The experimental evaluation shows that the FDFIR solution is very competitive in terms of performance, with a clear energy consumption advantage over the GPU solution.

Accelerating Persistent Scatterer Pixel Selection for InSAR Processing

Interferometric Synthetic Aperture Radar (InSAR) is a remote sensing technology used for estimating the displacement of an object on the ground or the earth's surface itself. Persistent Scatterer-InSAR (PS-InSAR) is a category of time series algorithms enabling high resolution monitoring. PS-InSAR relies on successful selection of points that appear stable across a set of satellite images taken over time. This paper presents PtSel, a new algorithm for selecting these points, a problem known as Persistent Scatterer Selection . The key advantage of PtSel over the key existing techniques is that it does not require model assumptions, yet preserves solution accuracy. Motivated by the abundance of parallelism the algorithm exposes, we have implemented it for GPUs. Our evaluation using real-world data shows that the GPU implementation not only offers superior performance but also scales linearly with GPU count and workload size. We compare the GPU implementation and a parallel CPU implementation: a consumer grade GPU offers 18x speedup over a 16-core Ivy Bridge Xeon System, while four GPUs offer 65x speedup. The GPU solution consumes 28x less energy than the CPU-only solution. Additionally, we present a comparison with the most widely used PS-interferometry software package StaMPS, in terms of point selection coverage and precision.

Chunked Bounding Volume Hierarchies for Fast Digital Prototyping Using Volumetric Meshes.

We present a novel approach to using Bounding Volume Hierarchies (BVHs) for collision detection of volumetric meshes for digital prototyping based on accurate simulation. In general, volumetric meshes contain more primitives than surface meshes, which in turn means larger BVHs. To manage these larger BVHs, we propose an algorithm for splitting meshes into smaller chunks with a limited-size BVH each. Limited-height BVHs make guided, all-pairs testing of two chunked meshes well-suited for GPU implementation. This is because the dynamically generated work during BVH traversal becomes bounded. Chunking is simple to implement compared to dynamic load balancing methods and can result in an overall two orders of magnitude speedup on GPUs. This indicates that dynamic load balancing may not be a well suited scheme for the GPU. The overall application timings showed that data transfers were not the bottleneck. Instead, the conversion to and from OpenCL friendly data structures was causing serious performance impediments. Still, a simple OpenMP acceleration of the conversion allowed the GPU solution to beat the CPU solution by 20 percent. We demonstrate our results using rigid and deformable body scenes of varying complexities on a variety of GPUs.

ODoST

Dynamic biomedical systems are mathematically described by Ordinary Differential Equations (ODEs) and their solution is often one of the most computationally intensive parts in biomedical simulations. With high inherent parallelism, hardware acceleration based on Field-Programmable Gate Arrays (FPGAs) has great potential to increase the computational performance of the model simulations, while being very power-efficient. However, the manual hardware implementation is complex and time consuming. The advantages of FPGA designs can only be realised if there is a general solution to automate the process. In this article, we propose a domain-specific high-level synthesis tool called ODoST that automatically generates an FPGA-based Hardware Accelerator Module (HAM) from a high-level description. In this direct approach, ODE equations are directly mapped to processing pipelines without any intermediate architecture layer of processing elements. We evaluate the generated HAMs on real hardware based on their resource usage, processing speed, and power consumption, and compare them with CPUs and a GPU. The results show that FPGA implementations can achieve 15.3 times more speedup compared to a single core CPU solution and perform similarly to an auto-generated GPU solution, while the FPGA implementations can achieve 14.5 times more power efficiency than the CPU and 3.1 times compared to the optimised GPU solution. Improved speedups are foreseeable based on further optimisations.

A novel heterogeneous algorithm to simulate multiphase flow in porous media on multicore CPU–GPU systems

Multiphase flow implementations of the lattice Boltzmann method (LBM) are widely applied to the study of porous medium systems. In this work, we construct a new variant of the popular “color” LBM for two-phase flow in which a three-dimensional, 19-velocity (D3Q19) lattice is used to compute the momentum transport solution while a three-dimensional, seven velocity (D3Q7) lattice is used to compute the mass transport solution. Based on this formulation, we implement a novel heterogeneous GPU-accelerated algorithm in which the mass transport solution is computed by multiple shared memory CPU cores programmed using OpenMP while a concurrent solution of the momentum transport is performed using a GPU. The heterogeneous solution is demonstrated to provide speedup of 2.6× as compared to multi-core CPU solution and 1.8× compared to GPU solution due to concurrent utilization of both CPU and GPU bandwidths. Furthermore, we verify that the proposed formulation provides an accurate physical representation of multiphase flow processes and demonstrate that the approach can be applied to perform heterogeneous simulations of two-phase flow in porous media using a typical GPU-accelerated workstation.

Solving the Caputo Fractional Reaction-Diffusion Equation on GPU

We present a parallel GPU solution of the Caputo fractional reaction-diffusion equation in one spatial dimension with explicit finite difference approximation. The parallel solution, which is implemented with CUDA programming model, consists of three procedures: preprocessing, parallel solver, and postprocessing. The parallel solver involves the parallel tridiagonal matrix vector multiplication, vector-vector addition, and constant vector multiplication. The most time consuming loop of vector-vector addition and constant vector multiplication is optimized and impressive performance improvement is got. The experimental results show that the GPU solution compares well with the exact solution. The optimized GPU solution on NVIDIA Quadro FX 5800 is 2.26 times faster than the optimized parallel CPU solution on multicore Intel Xeon E5540 CPU.

Parallelization Research of SapTis-Software of Multi-Field Simulation and Nonlinear Analysis of Complex Structures

SapTis is a software of simulation and nonlinear analysis of complex structures which based on the FEM method, this paper discussed the key technology of FEM parallelization and then the parallelization strategy of SapTis is given; There are three realization for the SapTis parallelization:Make fine grain parallelism to the PCG solution on the OpenMP platform; the other Krylov subspace method solutions and preconditioners was developed on the MPI platform; the sparse direct solutions was developed on the OpenMP platform. Test results show that there are high efficiency of the three parallel realization for SapTis, and each had its own characteristics. In addition, the GPU solution is still in development which will make the SapTis software more powerful, flexible and adaptable.

Perturbation Functions in Computer Graphics

The problem of real-time photorealistic imaging is discussed. New techniques for specifying free forms without their approximation by polygons are considered. Free forms based on the perturbation functions have an advantage of spline representation of surfaces, that is, a high degree of smoothness, and an advantage of arbitrary form for a small number of perturbation functions. Transformations of geometric objects are described for set-theoretic operations, projections, offsetting, and metamorphosis. We propose a GPU solution to render freeform objects at high frame rates.

Real-time, fast radio transient searches with GPU de-dispersion

The identification, and subsequent discovery, of fast radio transients through blind-search surveys requires a large amount of processing power, in worst cases scaling as $\mathcal{O}(N^3)$. For this reason, survey data are generally processed offline, using high-performance computing architectures or hardware-based designs. In recent years, graphics processing units have been extensively used for numerical analysis and scientific simulations, especially after the introduction of new high-level application programming interfaces. Here we show how GPUs can be used for fast transient discovery in real-time. We present a solution to the problem of de-dispersion, providing performance comparisons with a typical computing machine and traditional pulsar processing software. We describe the architecture of a real-time, GPU-based transient search machine. In terms of performance, our GPU solution provides a speed-up factor of between 50 and 200, depending on the parameters of the search.