Golden Reference Model Research Articles

Improved quantum circuit modelling based on Heisenberg representation

Heisenberg model allows a more compact representation of certain quantum states and enables efficient modelling of stabilizer gates operation and single-qubit measurement in computational basis on classical computers. Since generic quantum circuit modelling appears intractable on classical computers, the Heisenberg representation that makes the modelling process at least practical for certain circuits is crucial. This paper proposes efficient algorithms to facilitate accurate global phase maintenance for both stabilizer and non-stabilizer gates application that play a vital role in the stabilizer frames data structure, which is based on the Heisenberg representation. The proposed algorithms are critical as maintaining global phase involves compute-intensive operations that are necessary for the modelling of each quantum gate. In addition, the proposed work overcomes the limitations of prior work where the phase factors due to non-stabilizer gates application was not taken into consideration. The verification of the proposed algorithms is made against the golden reference model that is constructed based on the conventional state vector approach.

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

VLSI Architecture for Broadband MVDR Beamformer

Background/Objectives: The main objective of this proposed work is to investigate the significance of adaptive beamforming technique and to develop an efficient VLSI architecture for broadband MVDR beamformer in the field of medical ultrasound imaging. Methods/Statistical Analysis: The proposed algorithm is Minimum Variance Distortionless Response (MVDR) for near field beamforming of broadband data which gives better contrast and resolution compared to conventional Delay and Sum (DAS) beamformers and is implemented in frequency domain. MVDR beamformer minimizes the output power by allowing the desired signal to pass undistorted with unity gain. The solution for this optimization problem, involves correlation matrix inversion, which is the challenging part of MVDR algorithm. Findings: MVDR algorithm is applied by finding the inverse of correlation matrix which is a complex matrix. Here four elements are used for simplicity. Calculation of inverse complex matrix is the challenging part of MVDR algorithm where different methods are being used. Here QR decomposition is used which follows givens rotation algorithm. The paper demonstrates the formal verification of the proposed work. Final result is compared with the golden reference model which is designed using FIELD II scanner in Matlab. From the results it’s seen that, MVDR beamformer gives a pencil like beamform which shows high resolution and better contrast when compared to DAS. The timing constraints and device utilization parameters are obtained from synthesis report of final architecture designed in FPGA. Conclusion/Improvements: MVDR algorithm gives a pencil like beamformer output with reduced main lobe width and reduced side lobe level. By upgrading number of elements from 4 to 64, it can be made real time.

Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems

In this paper we present a new approach for automated target code generation for given real-time operating systems out of SystemC to support platform independent software development. Since SystemC becomes the most important language in electronic system level design, the support of a seamless design flow becomes an important task. During the system design process, SystemC is used to develop a "Golden Reference Model" that provides a well-suited platform for specification, simulation, and verification of embedded systems. Based on the "Golden Reference Model," an important task of the design process is to map applications, that have been described either in C++ or directly in SystemC, to the specific real-time operating system which is running at the target processor. Since a manual mapping approach is time-consuming and error-prone, the mapping process should be performed automatically. This paper presents a new method for automated generation of code for a specified operating system just by using an abstract XML representation of the RTOS API.

A methodology for validation of microprocessors using symbolic simulation

Functional validation is one of the most complex and expensive tasks in the current processor design methodology. A significant bottleneck in the validation of processors is the lack of a golden reference model. Thus, many existing approaches employ a bottom-up methodology by using a combination of simulation techniques and formal methods. We present a top-down validation approach using a language-based specification. The specification is used to generate the necessary reference models for processor validation using symbolic simulation. We applied our methodology for property checking as well as equivalence checking of microprocessors.

Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. A significant bottleneck in the validation of such systems is the lack of a golden reference model. Thus, many existing techniques employ a bottom-up approach to architecture validation, where the functionality of an existing pipelined architecture is, in essence, reverse-engineered from its implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through Architecture Description Language (ADL) constructs, and thus allows a powerful top---down approach to architecture validation. The most important requirement in top---down validation process is to ensure that the specification (reference model) is golden. Earlier, we have developed validation techniques to ensure that the static behavior of the pipeline is well-formed by analyzing the structural aspects of the specification using a graph based model. In this paper, we verify the dynamic behavior by analyzing the instruction flow in the pipeline using a Finite State Machine (FSM) based model to validate several important architectural properties such as determinism and in-order execution in the presence of hazards and multiple exceptions. We applied this methodology to the specification of a representative pipelined processor to demonstrate the usefulness of our approach.