Gold-tin Solder Research Articles

Design of Wafer Level Solder Seals – A Surface Energy Perspective

Wafer level vacuum packaging of quartz resonators and microelectromechanical system (MEMS) inertial sensors and RF switches have been successfully demonstrated by a number of investigators. The majority of these devices were sealed using reflow of gold-tin solder because of its superior hermeticity and benign processing conditions as compared to seals made using glass frit or anodic bonding. These successes have motivated efforts to integrate multiple sensors and active silicon devices within the same package to achieve improved performance and further reduce system size and cost. Sealing these large, heterogeneous assemblies at wafer level presents a more challenging problem than sealing small individual sensors, primarily due to wafer bow and irregularities in the seal surfaces. Wafer bow has been addressed in sealing wafers of individual sensors by plating metal stops adjacent to the seal rings, which allow the wafers to be pressed together to flatten the seal areas during bonding. This strategy cannot always be applied to sealing system devices because the amount of wafer bow is greater than that associated with more uniform wafers of sensors and the larger area of system devices increase the residual stress on the solder seal. An alternative approach to pressing wafers flat throughout the bond process would be to relax the force during reflow and allow the solder to bridge the nonplanar interface. We have used analytical and numerical calculations to investigate the interplay between seal width, height and shape of the seal gap, and solder volume associated with this bonding strategy. A set of soldering experiments were conducted on test articles that allowed us to independently vary these parameters to evaluate our model predictions.

High Thermal Conductive Die Attach Paste Using Polymer and Micron Size Silver for Power Semiconductor Package

Abstract Power semiconductor package manufactures and electronic device suppliers have been looking for Pb-free alternative to traditional high Pb solder die attach adhesives. Lead solders have high thermal conductivity, 30–50W/mK, and known process with some difficulties in high volume mass production such as void, bond line control, and requiring reducing atmosphere such as forming gas. Lead is now categorized as hazardous substance to human body and environment and its products are scheduled to be banned within a few years. Standard silver epoxy pastes and Electrically Conductive Adhesives (ECSs) are other forms of die attach adhesives but the thermal conductivity is not adequate for Power devices. Eutectic gold-tin solder (80Au20Sn) has 57W/mK but it is high cost material. Currently Silver sintering material has become popular for electronic device because it has high thermal conductivity (150~250W/mK) by using nano silver sintering. But it requires high bonding temperature and pressure. It makes brittle bonding structure and has limitation in die size due to high stress. New silver sintering material in this paper is composed of micron size silver and organic polymer. This technology overcomes all the limitations of conventional silver epoxy, eutectic gold thin solder and silver sintering product by using the unique design of polymer composition. This new silver sintering technology using polymer and micron size silver is a cost effective solution to replace Pb solder for power device and the thermal performance is almost same as nano silver sintering products. The application process is the same as standard silver epoxy and does not require new equipment. It is a cost effective drop in solution.

Power electronic assemblies: Thermo-mechanical degradations of gold-tin solder for attaching devices

The eutectic Au80Sn20 solder alloy has been applied in semiconductor assemblies and other industries for years. Due to some superior physical properties, Au/Sn alloy gradually becomes one of the best materials for soldering in electronic devices and components packaging but the voids growth in AuSn solder joints is one of the many critical factors governing the solder joint reliability. Voids may degrade the mechanical robustness of the die attach and consequently affect the reliability and thermal conducting performance of the assembly. Severe thermal cycles [−55°C/+175°C] have highlighted degradations in AuSn die attach solder. The inspection of as-prepared die-attachments by X-ray and SEM (observation of cross-section) shows that the initial voids sizes were increased and a propagation of transverse cracks inside the joint between voids has appeared after ageing, it was featured also the existence of the IMC typical scallop-shape morphology with the phase structure of (Ni, Au)3Sn2 on as-reflowed joints. In this paper, we evaluate the origin of these degradations and ways to address them.

Ultraviolet LED Multi-Chip Module Based on Ceramic Substrate

A high power ultraviolet (UV) light emitting diode (LED) multi-chip module package based on aluminum nitride (AlN) and alumina (Al2O3) is presented. The AlN substrate with a high thermal conductivity of up to 180 W/(m· K) and LED chips based on a copper alloy provide superb thermal management and heat extraction. Efficient cooling is an important prerequisite for the increase of extractable optical power and decrease of thermally induced wavelength shift. A design of a stackable module featuring arrays of 7×2 indium-gallium-aluminum- nitride UV LED chips at 395 nm is developed. This configuration of sub-modules allows for the scalable assembly of line sources with different lengths. Applications using UV LEDs cover market segments such as curing of adhesives, inks and coatings, sterilization of medical equipment and treatment of potable water, as well as various uses in chemical detection, biochemical analytics and spectroscopy. Thermal and thermo-mechanical modelling of the sub-mount is conducted using finite elements analysis. Die attach using eutectic gold-tin solder, lower melting tin-lead solder and silver-filled adhesive are compared with respect to optical output power and wavelength drift. Mechanical strength and structure of the resulting joints are investigated using shear force measurements, cross-sectioning and micro-tomography. An optical output power of 7.7 W is achieved using a cluster of 14 LED chips at 1050 mA resulting in a peak irradiance of 30.8 W/cm2 at the LED surface with respect to the footprint and pitch of the attached chips.

Die Bonding of High Power 808 nm Laser Diodes With Nanosilver Paste

Conduction-cooled high power laser diodes have a variety of significant commercial, industrial, and military applications. For these devices to perform effectively, an appropriate die-attached material meeting specific requirements must be selected. In this study, nanosilver paste, a novel die-attached material, was used in packaging the 60 W 808 nm high power laser diodes. The properties of the laser diodes operating in the continuous wave (CW) mode, including the characteristics of power–current–voltage (LIV), spectrum, near field, far field, near field linearity, spatial spectrum, and thermal impedance, were determined. In addition, destructive tests, including the die shear test, scanning acoustic microscopy, and the thermal rollover test, were conducted to evaluate the reliability of the die bonding of the 60 W 808 nm high power semiconductor laser with nanosilver paste. Thermal analyses of the laser diodes operating at CW mode with different die-attached materials, indium solder, gold–tin solder and nanosilver paste, were conducted by finite element analysis (FEA). According to the result of the FEA, the nanosilver paste resulted in the lowest temperature in the laser diodes. The test results showed that the nanosilver paste was a very promising die-attached material in packaging high power semiconductor laser.

Die-Attach Technologies for Ultraviolet LED Multichip Module Based on Ceramic Substrate

A high power UV light emitting diode (LED) multichip module package based on aluminum nitride (AlN) and alumina (Al2O3) is presented. The AlN substrate with a high thermal conductivity of up to 180 W/(m·K) and LED chips based on a copper alloy provide superb thermal management and heat extraction. Efficient cooling is an important prerequisite for the increase of extractable optical power and for the reduction of thermally induced wavelength shift. A design of a stackable module featuring arrays of 7×2 indium-gallium-aluminum-nitride UV LED chips at 395 nm is developed. This configuration of submodules allows for the scalable assembly of line sources with different lengths. Applications using UV LEDs cover market segments such as curing of adhesives, inks, and coatings, sterilization of medical equipment, and treatment of potable water, as well as various uses in chemical detection, biochemical analytics, and spectroscopy. Thermal and thermomechanical modeling of the submount is conducted using finite element analysis. Die attach using eutectic gold-tin solder, lower melting tin-lead solder, and silver-filled adhesive are compared with respect to optical output power and wavelength drift. Mechanical strength and structure of the resulting joints are investigated using shear force measurements, cross-sectioning, and microtomography. An optical output power of 7.7 W is achieved using a cluster of 14 LED chips at 1050 mA, resulting in a peak irradiance of 33.9 W/cm2 at the LED surface with respect to the footprint and pitch of the attached chips.

Effect of Bond Layer on Bimaterial Assembly Subjected to Uniform Temperature Change

When two thin plates or layers are bonded together, an extremely thin bond layer of third material exists between the two layers. This research work examines the effect of bond layer on the interfacial shearing and peeling stresses in a bimaterial model. Earlier papers on this topic are based on several mutually contradictory expressions for the shear compliance of the bond layer. This paper is aimed at resolving this ambiguity and presents derivation of shear compliance on a rational basis. A numerical example is carried out for a silicon-copper system with a gold-tin solder bond layer. The results obtained are likely to be useful in interfacial stress evaluation and physical design of bimaterial assemblies used in microelectronics and photonics applications.

Interfacial reaction between Au–Sn solder and Au/Ni-metallized Kovar

Gold-tin (Au–Sn) solder and Kovar alloy have been widely used in many fields such as mechanical engineering, atomic energy industry, aerospace facility, and electronic devices. Solder bonds strongly to the metallized substrate by forming intermetallic compounds (IMCs) at the interface. The IMC layer may adversely affect the reliability of the joints due to excessive growth and thermal fatigue during storage and service. Therefore, knowledge of the interfacial reactions between the Au–Sn solder and Au/Ni-metallized Kovar in microelectronic and optoelectronic packaging is essential. In this study, the microstructural evolution and interfacial reactions between the Au–Sn solder and Au/Ni-plated Kovar substrate were studied during aging at 180 and 250 °C for up to 1,000 h. The microstructure of the Au–Sn/Ni/Kovar joint was stable during aging at 180 °C. The solid-state interfacial reaction was much faster at 250 °C than at 180 °C. The joints aged at 250 °C fractured along the interface, thereby demonstrating brittle failure possibly because of the brittle IMC layer at the interface. The complete consumption of the thin Ni layer significantly weakened the joint interface during aging at 250 °C and clearly demonstrated the need for a thicker Ni layer in order to ensure the high temperature reliability of the Au–Sn/Ni/Kovar joint above 250 °C.

Layer Structure and Thickness Effects on Electroplated AuSn Solder Bump Composition

The eutectic gold-tin (AuSn) solder composition is receiving increased attention for packaging applications. In addition to the environmental benefits of removing lead compounds from electronic manufacturing, gold-tin eutectic also exhibits desirable mechanical properties such as high strength and low thermal fatigue. However, some methods of deposition for this solder require complicated processes or limit the minimum bump size. This paper explores the formation of AuSn eutectic solder bumps using sequential electrodeposition of Au and Sn to determine the effect of layer thickness and sequence on the composition and structure of the resulting solder bump

Sputtered full-wafer backside metallization for n-type InP: effect of temperature annealing

A full-wafer backside n-ohmic metallization scheme for InP is reported. The contact is formed by a single-step, all-sputter process and has been used successfully in three-inch InP opto-electronic device manufacturing. The metallization is based on the combination of a nickel–germanium–gold ohmic contact followed by a titanium–titanium nitride–titanium–gold metal stack. The titanium nitride layer acts as a barrier to grain boundary diffusion of indium and other material from the substrate to the surface of the top gold layer. The top gold is required for a gold–tin solder die bond process. The sputter process provides better than 5% cross-wafer and wafer-to-wafer thickness uniformity and a contact resistance of 2.5–8.3×10 −5 Ω cm 2. We report the fabrication process for this metal contact and the results of a full physical characterization by transmission electron microscopy, Auger survey and depth profile analysis and X-ray analysis.

Extraction of bonding strain data in diode lasers from polarization-resolved photoluminescence measurements

A technique to determine strain in diode lasers by matching measured polarization-resolved photoluminescence to a finite element method model is described. The code is shown to be able to fit well a finite element model with degree of polarization measurements to extract strain information from diode lasers and predict strain values owing to die bonding. It is useful in characterizing die bonding processes and in detecting solder voids which can impact the reliability of devices. Using the code, it is demonstrated that there are differences in the die bonding strain from different die attachments. The bonding strain from InP chips die bonded to copper and silicon chip carriers using gold–tin solder are examined.

A silicon optical bench incorporating a tantalum-nitride thin-film resistor

A new silicon optical bench (SiOB)—incorporating tantalum-nitride thin-film resistors (TNTFRs) for signal damping as well as terminating transmitted signals—has been developed. The SiOB has a deep V-groove for locating a lens, gold/platinum/titanium thin-film electrodes and gold–tin solder films for mounting a laser diode and a photodiode. The tantalum-nitride thin film for the TNTFRs is deposited by RF-magnetron reactive sputtering. The film was analyzed by both Auger electron spectroscopy and x-ray diffraction, and its composition is identified as Ta2N. The measured V-grooves have an average width of 1000.8 µm with 3σ variation of 1.2 µm. This result indicates that silicon anisotropic etching using fan-shaped patterns can fabricate precise V-grooves without producing crystal deviation. Moreover, the TNTFRs for damping have an average resistance of 9.74 Ω, a breakdown-current density of 2.00 × 1010 A m−2 and a temperature coefficient of resistance of 106 ppm °C−1; the corresponding values of TNTFR for termination are 48.1 Ω, 2.58 × 1010 A m−2 and 108 ppm °C−1. And the average change in resistance for damping after conducting reliability tests is less than 1.97%. Consequently, the developed SiOB is suitable for use in transmitter modules because it has precise V-grooves and TNTFRs with a low-variability resistance.

Design and fabrication of thin film resistive heaters for hybrid optoelectronic packaging

This paper presents the technology for the design and fabrication of planar resistive heaters made from vacuum deposited nichrome thin films on a quartz substrate. These heaters are suitable as isolated local heat sources for melting solder to attach discrete components on a hybrid optoelectronic integration platform. Numerical simulations are performed using the Finite Element Method (FEM) to determine the geometry of the heaters in order to deliver adequate thermal performance. Multiple heater elements are batch processed on a 3.0 in polished fused quartz wafer using standard photolithographic techniques. Use of polyimide as a reliable insulation layer between the nichrome thin film and the solder has improved the thermal uniformity over the heater surface. Individual heaters can reach temperatures close to 300/spl deg/C drawing 7.1 W of power on an uncooled alumina platform and 12.0 W on an uncooled copper platform. This temperature is high enough to melt gold-tin (AuSn) solder (with eutectic melting point of 280/spl deg/C), typically used for attaching different optoelectronic components on a substrate.

Comments on Quantifying the Results of Electron-Probe Analysis of a Gold-Tin Solder

Abstract First, it is important to know whether the objective of the analysis is to measure the total amount of the two metals in the assembly as a whole, or to measure their proportions in each of the different areas; the tin solder, the intermetallic layers and so on. The purpose to which the results are to be put is also important. To some extent the answer depends on knowing this, as a biased but highly repeatable measure of something is often useful for internal purposes. For Au/Sn intermetallic compounds which have quite specific compositions, the absorption/enhancement effects will be different than for a low-concentration solid solution of either of the metals in the other.

Electroplated electro-fluidic interconnects for chemical sensors

A wet chip electro-fluidic packaging technology based on electroplating is described. An electroplated gold seal provides the sensor's fluid connection to a silicon multi-chip module. A hermetic seal is obtained using the gold–silicon eutectic bond. The sensor's electrical connections to the multi-chip module are made by eutectic bonding electroplated gold–tin solder bumps on the sensor to gold pads on the substrate. The fluid and electrical connections are made simultaneously, and the process is compatible with the flip-chip bonding technique.

LSI Packaging that Passes PIND Test

A packaged large-scale integrated (LSI) chip or hybrid destined for military or space applications must pass the gambit of screens listed in Method 5004 of MIL-STD-883B. These screens include the particle impact noise detection (PIND) test in which a sensitive acoustic transducer listens for loose particles inside a package while the package is vibrated and shocked. Prior to instituting new assembly procedures, PIND test yields were as low as 20 percent. We have used scanning electron microscopy (SEM) and energy dispersive analysis X-rays (EDAX) [1] to identify the particles that caused PIND test failures and have developed and are now using assembly procedures that result in a low reject rate at PIND testing. With these procedures, 3099 packages have been PIND tested with 155 failures noted, resulting in yields that exceed 94 percent. The assemblies consisted of a 1 K random access memory (RAM) die with dimensions of 3.5 x 6.1 x 0.031 mm thick which is attached with gold/silicon eutectic to a 24-pin leadless hermetic package. Packages were solder sealed in a belt furnace with a gold-tin eutectic alloy preform and a nickel and gold plated Kovar lid. The major particle type which caused PIND test failures was determined to be gold-tin spheres from the gold-tin preform. To a much lesser degree, other particles such as calcium silicate, gold, and silicone were noted. The effect of furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder balls detected in the sealed packages was investigated. The best results were obtained if the sealing furnace ambient was nonoxidizing, peak temperature was approximately 360°C, and the packages were sealed in a 45° lid down position.