Gigabit Interface Research Articles

Quality of Service on Link Aggregation Network Virtualization for Docker Containers

Docker engine is an extremely powerful tool for PaaS platform of cloud computing. It gives benefits for large-scale of internet services. Web service is basic service for everyone who requires to access internet that web infrastructure must has scalability with load-balance web server called reverse proxy. The key answers for a large-scale web must have multiple web servers working together with high speed bandwidth. Moreover, multiple clusters can find in the same data center there are required to assign priority and quality of each cluster service. We investigate load-balance assign link aggregation with network QoS by using pipework script and traffic control tool in frontend reverse proxy server on each cluster. Our research evaluates scenario of network QoS ratios which include 50/50, 60/40, 70/30 and 80/20. We compare network bandwidth between both web reverse proxy clusters. The results present our designed and implementation tool not only can control network QoS on each web reverse proxy cluster in all load-balance link aggregation modes which include round-robin, XOR and ALB but also those of clusters can access multiple network interface. In experiment, average network bandwidths in all QoS cases are around 200 MB per second for link aggregation of 2 gigabit interface.

An FPGA Based General Purpose DAQ Module for the KLOE-2 Experiment

A general purpose FPGA based DAQ module has been developed based on a Virtex-4 FPGA. It is able to acquire up to 1024 different channels distributed over 10 slave cards. The module has an optical interface a RS-232 a USB and a Gigabit Interface. The KLOE-2 experiment is going to use it to collect data from the Inner tracker and the QCALT. An embedded processor (power pc 604) is present on the FPGA and a telnet server has been developed and installed. A new general purpose data taking system has been based on this module to acquire the Inner Tracker. The system is at the moment working at LNF (Laboratori Nazionali di Frascati).

An FGPA Based General Purpose DAQ Module for the KLOE-2 Experiment

A general purpose FPGA based DAQ module has been developed. This module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 10 slave cards. The module has an optical interface, a RS-232 port, a USB and a Gigabit Interface. The KLOE-2 experiment is going to use this module to acquire data from the Inner tracker. An embedded processor (Power PC) is present on the FPGA and a telnet server has been developed and installed. A new general purpose data taking system has been based on this new module to acquire the Inner Tracker. The system is presently working at LNF (Laboratori Nazionali di Frascati).

A Scalable Architecture for Network Traffic Monitoring and Analysis Using Free Open Source Software

The lack of current network dynamics studies that evaluate the effects of new application and protocol deployment or long-term studies that observe the effect of incremental changes on the Internet, and the change in the overall stability of the Internet under various conditions and threats has made network monitoring challenging. A good understanding of the nature and type of network traffic is the key to solving congestion problems. In this paper we describe the architecture and implementation of a scalable network traffic moni-toring and analysis system. The gigabit interface on the monitoring system was configured to capture network traffic and the Multi Router Traffic Grapher (MRTG) and Webalizer produces graphical and detailed traffic analysis. This system is in use at the Obafemi Awolowo University, IleIfe, Nigeria; we describe how this system can be replicated in another environment.

Data acquisition board with optical gigabit interface

The precision vertex tracker, based on the technology of active CMOS pixel sensors, is a proposed addition to the tracking system of the STAR experiment . The proposed tracker consists of two cylindrical layers formed by 24 ladders. Each ladder contains a row of 10 monolithic CMOS detector chips and each chip has a 640 /spl times/ 640 array of 30 micron square pixels. The total number of pixels is 0.98/spl times/10/sup 8/. The mission critical tasks for this detector are data reduction and data transfer. Different approaches to implementation of the data acquisition system (DAQ) are under consideration. The approach discussed in this paper is to use commercially available components, like FPGAs, on the detector side and commercial Ethernet modules on the host computer side. A prototype DAQ board has been designed, manufactured and is in use for system development and testing. In this paper, the data transfer is discussed in details, including the concept, the protocol and data transfer rates.

Spinach

This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are common to all programmable environments (e.g., ALUs, control and data paths, registers, instruction processing) and components that are specific to the embedded systems and network interface environments (e.g., software-controlled scratchpad memory, hardware assists for DMA and medium access control).Spinach is built on the Liberty Simulation Environment (LSE) and exploits LSE's modularity to support easy reconfiguration of programmable network interface cards (NICs) and embedded systems, enabling wide design space exploration with little or no code variation. For example, the same underlying C code is used whether supporting a uniprocessor Gigabit network interface, a multiprocessor Gigabit interface, or a multiprocessor 10 Gigabit interface with a highly heterogeneous memory system. The only difference is in a small number of lines of high-level scripting code used to configure the various modules into a simulation model.Spinach is validated by modeling the Tigon-2 programmable Ethernet controller by Alteon Websystems running actual Ethernet processing firmware and by comparing the reported results to actual hardware benchmarks. Spinach is then used to obtain new insights about the performance of Gigabit and 10 Gigabit network interfaces.