Gigabit Ethernet Transceiver Research Articles

White Rabbit Clock Synchronization: Ultimate Limits on Close-In Phase Noise and Short-Term Stability Due to FPGA Implementation

This paper investigates the ultimate limits of White Rabbit (WR), an high-accuracy time distribution system based on field-programmable gate array (FPGA). The knowledge of such limits is essential for new emerging applications that are evaluating WR. In this paper, we identify and study the key elements in the WR synchronization: the digital dual mixer time difference phase detector and the Gigabit Ethernet transceiver. The benchmarks and experimental analysis of these key elements allow us to determine the WR switch (WRS) performance limits and evaluate their evolution with newer FPGAs. The identified performance limits are achievable by the present-day generation of WRS. The ultimate limits of short-term synchronization performance due to FPGA implementation have been derived through analysis and then demonstrated using the existing WRS enhanced with an additional daughterboard. This combination (WRS and daughterboard) achieves a tenfold improvement in terms of phase noise, jitter, and short-term stability with respect to the current WR performance. Both phase detectors and Gigabit transceivers have a similar phase noise contribution equal to a short-term stability of modified Allan deviation 4E-13 at $\tau = 1$ s (dominated by flicker phase modulation noise).

Performance of Pad Front-End Board for Small-Strip Thin Gap Chamber With Cosmic Ray Muons

We report on the characterization of pad front-end board (pFEB) for small-strip thin gap chamber (sTGC) prototype. The pFEB is based on field programmable gate array (FPGA) and application-specific integrated circuit. It has been built to verify the capabilities of the sTGC detector for the ATLAS Phase-I new small wheel upgrade. The pFEB consists of three VMM2 front-end chips, two Kintex-7 FPGAs used to buffer the VMM2 data, a gigabit ethernet transceiver (GET), and all the required connectors. The VMM2, designed at Brookhaven National Laboratory, is composed of 64 linear front-end channels. Each channel integrates a charge sensitive amplifier, a shaper, a stable band-gap referenced baseline, several analog-to-digital converters, and other functions. The GET works at physical layer of the network. The mini-serial attached SCSI connector accepts three external signals (40-MHz clock, reset, and trigger), which are used for synchronization of several pFEBs. In addition, the pFEB can work in the case of self-trigger mode and external trigger mode. The specific characteristics and implementations are described in detail. Also, the performance of this new type of sTGC detector has been studied with cosmic ray muons.

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV $_{\rm ppd}$ to 1.06 V $_{\rm ppd}$ . RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 $^{-12}$ is 42 mV $_{\rm ppd}$ . The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 $^{-15}$ on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

The RF Amplifier Remote Monitoring System Based on Gigabit Ethernet

Based on the Gigabit Ethernet Protocol, the RF (Radio Frequency) power amplifier remote monitoring system was designed. The system collect digital signal from predistortion module, transmit the gigabit Ethernet network to outside, and improve the system efficiency. It adopts the SOPC technology hardcore and softcore, which makes the whole system realized in the single piece of chip. Softcore is the Alteras IP core--Nios II processor, design processors, make use of the custom parts and programs gigabit Ethernet transceiver and internal driving in processor. The integration and reliability of the system are in great improvement. Through testing, system function can satisfy transmission requirements of normal transceiver RF power amplifier state information and control information.

High-performance, low-cost joint equalizer and trellis decoder for 1000BASE-T gigabit Ethernet transceiver

This article presents an M-algorithm (MA) decoder with 4 survival paths (MA4) for Institute of Electrical and Electronics Engineers (IEEE) 802.3ab 1000BASE-T gigabit Ethernet (GbE) transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and 1 Gb/s throughput in 1.8 V 0.18 μm standard cell complementary metal-oxide-semiconductor (CMOS) process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder (PDFD) with 39% area reduction.

Multichannel bit error rate tester for fiber optic transceiver testing

I describe an inexpensive and portable method used to conduct bit error rate test measurements in an aircraft at altitude to measure susceptibility of gigabit fiber optic transceivers to ionizing radiation. This method uses a built-in test feature of Texas Instruments GigaBit Ethernet transceiver chips. During a 20 min flight at 39 000 ft altitude, none of the eight test channels using Finisar FTRJ-8519-1 fiber optic transceivers indicated any bit errors.