Giga Samples Per Second Research Articles

Development of a prototype 16-channel dual gain waveform readout and data transfer system for IACT based telescope camera

A 256-pixel camera for a 4-meter class telescope based on Imaging Atmospheric Cherenkov Technique (IACT) is under development. It would be mounted at the focal plane of TeV Atmospheric Cherenkov Telescope with Imaging Camera (TACTIC) array element at Mount Abu (Rajasthan, India). The telescope would be used for detection of very high energy gamma rays of celestial origin. Instead of the traditional choice of photo-multiplier tube, the camera employs silicon photo-multiplier (SiPM) as pixel sensor. The front-end electronics of the camera processes signals from 256 pixel sensors. The back-end electronics samples the processed pixel signals, generates event triggers and records the sampled signals. The critical design objectives to be met by the back-end electronics include large dynamic range of photon detection, capability of in-situ gain calibration for each pixel chain, low chance trigger rate, recording the pixel signal profile with a sampling rate of 1 Giga Samples Per Second (GSPS), low dead time (<1 millisecond) and run-time control of the camera operation. Also, the camera cost, power, size and weight should be as low as possible. The important back-end tasks like pixel signal processing, generating pre-triggers, digitization of the pixel pulse profiles, packing and sending the digitized data are performed by the custom designed Cluster Digitizer Module (CDM). CDM is a 16-channel readout system, and its design revolves around an ultra-fast analog sampler chip and a set of FPGAs. The CDM is thoroughly tested in the lab using test signals from SiPM as well as high performance function generator. The paper describes the design, development and performance of the prototype CDM.

Frequency Domain Multiplexing for Microwave Kinetic Inductance Detectors: Comparing the Xilinx ZCU111 RFSoC with the New 2x2 RFSoC Board

The Xilinx ZCU111 Radio Frequency System on Chip (RFSoC) is a promising solution for reading out large arrays of microwave kinetic inductance detectors (MKIDs). The board boasts eight on-chip 12-bit / 4.096 GSPS analogue-to-digital converters (ADCs) and eight 14-bit / 6.554 GSPS digital-to-analogue converters (DACs), as well as field programmable gate array (FPGA) resources of 930,000 logic cells and 4,272 digital signal processing (DSP) slices. While this is sufficient data converter bandwidth for the readout of 8,000 MKIDs, with a 2 MHz channel-spacing, and a 1 MHz sampling rate (per channel), additional FPGA resources are needed to perform the DSP needed to process this large number of MKIDs. A solution to this problem is the new Xilinx RFSoC 2x2 board. This board costs only one fifth of the ZCU111 while still providing the same logic resources as the ZCU111, albeit with only a quarter of the data converter resources. Thus, using multiple RFSoC 2x2 boards would provide a better balance between FPGA resources and data converters, allowing the full utilization of the RF bandwidth provided by the data converters, while also lowering the cost per pixel value of the readout system, from approximately EUR2.50 per pixel with the ZCU111, to EUR1 per pixel.

Characterizing the performance of high-speed data converters for RFSoC-based radio astronomy receivers

ABSTRACT RF system-on-chip (RFSoC) devices provide the potential for implementing a complete radio astronomy receiver on a single board, but performance of the integrated analogue-to-digital converters (ADCs) is critical. We have evaluated the performance of the data converters in the Xilinx ZU28DR RFSoC, which are 12-bit, 8-fold interleaved converters with a maximum sample speed of 4.096 Giga-sample per second (GSPS). We measured the spurious-free dynamic range (SFDR), signal-to-noise and distortion (SINAD), effective number of bits (ENOB), intermodulation distortion (IMD), and cross-talk between adjacent channels over the bandwidth of 2.048 GHz. We both captured data for off-line analysis with floating-point arithmetic, and implemented a real-time integer arithmetic spectrometer on the RFSoC. The performance of the ADCs is sufficient for radio astronomy applications and close to the vendor specifications in most of the scenarios. We have carried out spectral integrations of up to 100 s and stability tests over tens of hours and find thermal noise-limited performance over these time-scales.

A broadband digital receiving system with large dynamic range for solar radio observation

Solar radio spectra and their temporal evolution provide important clues to understand the energy release and electron acceleration process in the corona, and are commonly used to diagnose critical parameters such as the magnetic field strength. However, previous solar radio telescopes cannot provide high-quality data with complete frequency coverage. Aiming to develop a generalized solar radio observing system, in this study, we designed a digital receiving system that could capture solar radio bursts with a broad bandwidth and a large dynamic range. A dual-channel analog-to-digital converter (ADC) printed circuit board assembly (PCBA) with a sampling rate of 14-bit, 1.25 Giga samples per second (GSPS) cooperates with the field-programmable-gate-array (FPGA) chip XC7K410T in the design. This receiver could realize the real-time acquisition and preprocessing of high-speed data of up to 5 GB s−1, which ensures high time and spectral resolutions in observations. This receiver has been used in the solar radio spectrometer working in the frequency range of 35 to 40 GHz in Chashan Solar Observatory (CSO) established by Shandong University, and will be further developed and used in the solar radio interferometers. The full-power bandwidth of the PCBA in this receiving system could reach up to 1.5 GHz, and the performance parameters (DC–1.5 GHz) are obtained as follows: spur free dynamic range (SFDR) of 64.7–78.4 dB, signal-to-noise and distortion (SINAD) of 49.1–57.2 dB, and effective number of bits (ENOB) of > 7.86 bit. Based on the receiver that we designed, real-time solar microwave dynamic spectra have been acquired and more solar microwave bursts with fine spectral structures are hopeful to be detected in the coming solar maximum.

Exploring the sampling rate effect on digital time of flight response for fast scintillator detectors

A systematic study is conducted to understand the digital time of flight (TOF) response for a pair of fast scintillator detectors; BaF2–LaBr3, BaF2-BC501A, and LaBr3-BC501A respectively. Coincidence signals from each detector pair, irradiated by 22Na source, are acquired by LeCroy HDO5000A digital oscilloscope. While operating the oscilloscope at 2.5 giga samples per second (GSPS) and 500 mega samples per second (MSPS) of sampling rates, over 10 k coincidence signals were collected for each pair of detectors. Data at different sampling rates; 1.66 GSPS, 1.25 GSPS, 833 MSPS, 625 MSPS, 333 MSPS, and 250 MSPS were generated by down-sampling method. Using anode signal, the photon arrival time marker is determined by digital constant fraction (DCF) algorithm for each detector pair on event-by-event basis. For a given rate, the algorithm is optimized at various delay and fraction values to get the minimum TOF dispersion. Mentioned pairs reveals the TOF resolution (FWHM) as; 0.58 ns, 0.79 ns, 0.907 ns and 0.53 ns, 0.94 ns, 1.08 ns at 250 MSPS and 2.5 GSPS respectively. While analysing the events, a saturation in the TOF width is observed from 500 MSPS onward. The saturated dispersion values for the aforementioned pairs are found to be 0.53 ns, 0.94 ns, and 1 ns respectively. Effect is being understood by calculating the optimum DCF transition region distribution for BC501A and LaBr3 detectors, reveals a constant curvature profile at different rates. To further explain the saturation effect on computational ground, a simple pulse fitting approach is adopted using Landau distribution. Event-by-Event processing of fitted pulses followed by TOF resolution calculation reproduces the experimental numbers.

Fast pulse sampling module for real-time neutron–gamma discrimination

An adaptable and compact fast pulse sampling module was developed for the neutron–gamma discrimination. The developed module is well suited for low-cost and low-power consumption applications. It is based on the Domino Ring Sampler 4 (DRS4) chip, which offers fast sampling speeds up to 5.12 giga samples per second (GSPS) to digitize pulses from front-end detectors. The high-resolution GSPS data is useful for obtaining precise real-time neutron–gamma discrimination results directly in this module. In this study, we have implemented real-time data analysis in a field programmable gate array. Real-time data analysis involves two aspects: digital waveform integral and digital pulse shape discrimination (PSD). It can significantly reduce the system dead time and data rate processed offline. Plastic scintillators (EJ-299-33), which have proven capable of PSD, were adopted as neutron detectors in the experiments. A photomultiplier tube (PMT) (model #XP2020) was coupled to one end of a detector to collect the output light from it. The pulse output from the anode of the PMT was directly passed onto the fast sampling module. The fast pulse sampling module was operated at 1 GSPS and 2 GSPS in these experiments, and the AmBe-241 source was used to examine the neutron–gamma discrimination quality. The PSD results with different sampling rates and energy thresholds were evaluated. The figure of merit (FOM) was used to describe the neutron–gamma discrimination quality. The best FOM value of 0.91 was obtained at 2 GSPS and 1 GSPS sampling rates with an energy threshold of 1.5 MeVee (electron equivalent).

Prototype readout system for a multi Mpixels UV single-photon imaging detector capable of space flight operation

Our collaboration works on the development of a large aperture, high resolution, UV single-photon imaging detector, funded through NASA's Strategic Astrophysics Technology (SAT) program. The detector uses a microchannel plate for charge multiplication, and orthogonal cross strip (XS) anodes for charge readout. Our target is to make an advancement in the technology readiness level (TRL), which enables real scale prototypes to be tested for future NASA missions. The baseline detector has an aperture of 50×50 mm and requires 160 low-noise charge-sensitive channels, in order to extrapolate the incoming photon position with a spatial resolution of about 20 μm FWHM. Technologies involving space flight require highly integrated electronic systems operating at very low power. We have designed two ASICs which enable the construction of such readout system. First, a charge sensitive amplifier (CSAv3) ASIC provides an equivalent noise charge (ENC) of around 600 e−, and a baseline gain of 10 mV/fC. The second, a Giga Sample per Second (GSPS) ASIC, called HalfGRAPH, is a 12-bit analog to digital converter. Its architecture is based on waveform sampling capacitor arrays and has about 8 μs of analog storage memory per channel. Both chips encapsulate 16 measurement channels. Using these chips, a small scale prototype readout system has been constructed on a FPGA Mezzanine Board (FMC), equipped with 32 measurement channels for system evaluation. We describe the construction of HalfGRAPH ASIC, detector's readout system concept and obtained results from the prototype system. As part of the space flight qualification, these chips were irradiated with a Cobalt gamma-ray source, to verify functional operation under ionizing radiation exposure.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

Analysis on multiple-component synchronization of ultra-fast time-interleaved analog-to-digital conversion systems and its novel parameterized hardware solution.

Parallelism-based technique of time-interleaved analog-to-digital conversion (TIADC) has become an effective solution for the higher sampling rate acquisition system to acquire non-repetitive waveforms. With the increase of sampling frequency, the indeterminacy of combining sequence of sampled data among multiple components has become a highlighted barrier for the reset operation of high-speed acquisition systems, and this is especially obvious for the ultra-fast TIADC systems. In this paper, we clarify the root of the problem in multiple-component synchronization (MCS) caused by such reset operation. Also we propose a novel and reliable hardware solution to precisely condition each reset signal, including three key circuit design parameters, i.e., the best time interval, required edge uncertainty, and the minimum delay precision. Besides, the designing scheme and debugging procedures are presented in detail in a generalized platform of this system type. Finally, in order to demonstrate the feasibility, parametric materialization and testing verification are gradually accomplished in a 20 Giga Samples Per Second (GSPS) TIADC system composed of four 5 GSPS ADC components. The results show that the proposed method is feasible and effective for ensuring the combined determinacy of multiple groups of sampled data and solving the MCS problem. In comparison with other existing solutions, it adopts some simple logic components more easily and flexibly, and this is significant for the development of congeneric systems or instruments featuring the MCS.

Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators

A three gigasample per second (GSPS) digital wideband receiver that operates in a 1.25-GHz instantaneous bandwidth (IBW) is proposed. In addition to building such systems, offloading of computation-intensive tasks to a combination of specialized hardware accelerators such as graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) to increase the overall receiver's dynamic performance is analyzed. The receiver detects up to 15 signals with a maximum attainable instantaneous dynamic range (IDR) of 62.5 dB before the next set of data arrives for processing.

Towards Low Cost, High Speed Data Sampling Module for Multifunctional Real-Time UWB Radar

There is a need for the development of a low cost, low jitter, fast processing hardware for various ultrawideband (UWB) radar applications, such as dynamic real-time imaging and micro-Doppler human motion detection with high range resolution. Achieving such high range resolution is typically limited by the availability of low cost gigahertz sampling speed electronics. In order to achieve dynamic real-time imaging, a fast refresh rate and high-speed processing are essential, but they are typically very expensive and difficult to obtain. To circumvent the need for these very expensive processors, an equivalent time sampling method has been successfully applied to implement a compact data acquisition module with a low cost solution. The developed integrated compact module supports dual sampling channels with a maximal 100 giga-samples per second (GSPS) equivalent time sampling rate and relatively low jitter. The equivalent time sampling technique achieves a relatively high effective capture rate, however, this is at a cost of complicated timing control logic and sampled data reconstruction. The developed module includes a novel, robust, efficient, low-jitter data preprocessing scheme implemented in field-programmable gate arrays (FPGAs), and a faster back projection method based on look-up table for real-time 2D imaging. In the work presented here, the design details of the newly developed system as well as its performance are discussed. Various examples of utilizing the developed radar for real-time high resolution target imaging and micro-Doppler detection are also presented.

A Scalable DAQ System Based on the DRS4 Waveform Digitizing Chip

Many current and future experiments require the highest temporal resolution together with large numbers of channels in the data acquisition system (DAQ) for a minimum cost. The DRS4 waveform digitizing chip allows data sampling at up to 5 Giga-samples per second (GSPS) with high amplitude resolution. The domino wave sampling method offers a significant cost and power reduction compared to a traditional flash analog-to-digital converter (ADC). This work presents a new DAQ system based on the DRS4 chip that allows continuous digitization of analog signals at 120 Mega-samples per second (MSPS) with the possibility to sample a region of interest up to a rate of 5 GSPS, thereby allowing a long event record with small dead-time in the read-out. The signal-to-noise ratio (SNR) of the system is measured to be 9.3 bit for the 120 MSPS signal and 9.6 bit for the DRS4 readout signal. Arbitrarily complex trigger logic can be built entirely in the digital domain in the read-out field-programmable gate array (FPGA). A Gigabit Ethernet link provides high-speed connectivity from the DAQ board to the backend system. Built-in board-to-board communication and the modular design of the system offer great scalability and flexibility with respect to the number of supported data channels.

Application of the DRS chip for fast waveform digitizing

The high demands of modern experiments in fast waveform digitizing led to the development of a whole family of switched capacitor arrays (SCA), called the Domino Ring Sampler (DRS). The most recent version, DRS4, is produced in a radiation hard 0.25μm CMOS process, and is capable of digitizing 9 differential input channels at sampling rates of up to 6 Giga-samples per second (GSPS) with an analogue bandwidth of 950MHz (−3dB). The channel depth can be configured between 1024 and 8192 cells, and the signal-to-noise ratio allows a resolution equivalent to more than 11 bits. Using an interleaved sampling technique, sampling rates up to 48 GSPS are possible. Compared with the previous versions, the DRS4 chip contains several improvements such as an on-chip PLL for sampling-frequency stabilization and various mechanisms to reduce the read out dead-time. The high bandwidth, low power consumption and short readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs. This includes time-of-flight detectors, cosmic gamma ray observatories, PET scanners and industrial applications.

Design and Performance Evaluation of a 2.5-GSPS Digital Receiver

Today's very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

Digitally linearized wide-band photonic link

A photonic analog-to-digital (A/D) link with third-order distortion suppression is proposed and demonstrated. Experimental results with single-and two-tone analog input signals and a one giga-sample per second (GSPS) photonic A/D system with 500-MHz instantaneous bandwidth are presented. The application of a simple time-domain linearization scheme results in distortion suppression approaching 30 dB and allows optical modulation depths over 80%.

Highly parallel pulsed optoelectronic analog-digital converter

We characterize the performance of a highly parallel pulsed optoelectronic analog to digital converter. The system is based on a time-domain to wavelength-domain mapping, such that an input analog signal is parallelized using a wavelength-division-demultiplexed scheme. Each parallel wavelength channel is then digitized using conventional, slow electronic analog-digital converters. We use narrow-band signals up to 18 GHz and histogram testing to characterize the system. From the measurements, we deduce the effective number of bits of the system to be /spl sim/6 and /spl sim/5 bits for 4 and 36 giga-samples-per-second (GSPS) sampling rates, respectively.