GHz Wideband Power Amplifier Research Articles

A 24–30 GHz 31.7% Fractional Bandwidth Power Amplifier With an Adaptive Capacitance Linearizer

A two-stage 24-30 GHz wideband power amplifier (PA) with an adaptive capacitance linearizer is presented, which is fabricated using a 28-nm bulk CMOS process. Staggered input gain matchings of the driver and power stages are implemented with wideband output power matchings to achieve wideband power characteristics. An adaptive capacitance linearizer is introduced at the power stage input to improve the AM-PM linearity with respect to input powers. At 24/26/28/30 GHz, it achieves 19.7/20.3/20/20 dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> , 18.2/18.2/17.8/17.2 dBm P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , and 34.5/33.1/30/30.3% peak power added efficiency (PAE). The small-signal gain of 21.2 dB and the 3-dB bandwidth of 8.2 GHz are achieved. It has a core size of 0.189 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

6-18 GHz Reactive Matched GaN MMIC Power Amplifiers with Distributed L-C Load Matching

A commercial 0.25 μm GaN process is used to implement 6–18 GHz wideband power amplifier (PA) monolithic microwave integrated circuits (MMICs). GaN HEMTs are advantageous for enhancing RF power due to high breakdown voltages. However, the large-signal models provided by the foundry service cannot guarantee model accuracy up to frequencies close to their maximum oscillation frequency (Fmax). Generally, the optimum output load point of a PA varies severely according to frequency, which creates difficulties in generating watt-level output power through the octave bandwidth. This study overcomes these issues by the development of in-house large-signal models that include a thermal model and by applying distributed L-C output load matching to reactive matched amplifiers. The proposed GaN PAs have successfully accomplished output power over 5 W through the octave bandwidth.

A compact, 36 to 72 GHz 15.8 dBm power amplifier with 66.7% fractional bandwidth in 45 nm SOI CMOS

ABSTRACTA 36 to 72 GHz wideband power amplifier (PA) in 45‐nm silicon‐on‐insulator CMOS is presented. The PA adopts a two‐stage cascode topology, in which counterposed resonances in the matching networks enable a 3‐dB output power bandwidth of 36 GHz. This bandwidth represents a 66.7% fractional bandwidth—a 1.8X improvement over previously reported CMOS V‐band PAs. At 62 GHz, the PA achieves a peak output power of 15.8 dBm, a gain of 16.9 dB, and 9.4% power‐added efficiency using a 2.2‐V supply. The PA has the largest output power and smallest die area among reported wideband (BW &gt; 30%) millimeter‐wave PAs in CMOS. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:166–169, 2014

Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process

The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.

2–4 GHz wideband power amplifier with ultra‐flat gain and high PAE

Demonstrated is a 2–4 GHz wideband power amplifier (WPA) using Cree 10 W GaN HEMT CGH40010. Also a novel process to find the optimum impedances is presented, with which the gain flatness can be taken into account. A compact PCB has been fabricated and tested with continuous waves at low (20 dBm) and high (28 dBm) input power level. From the measured results, at low power level, the gain is 13.1–14.1 dB across 2.0–3.9 GHz and 12.3–14.1 dB across 2.0–4.0 GHz. For large signals, power gain is 11.1–12.6 dB with power-added efficiency (PAE) 36.5–53.4% while output power is around 40 dBm. Gain flatness keeps less than 1 dB beyond 95% of the band. For a 5 MHz WCDMA signal, the adjacent channel leakage ratio of the WPA with digital predistortion reaches − 45.3 dBc with an average drain efficiency of 46.7%.

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 13.8 dBm, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> biased at 1.8 V. When V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> is biased at 3 V, it exhibits P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 18 dBm, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.