GHz Voltage-controlled Oscillator Research Articles

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

An integrated spiral DGS and an open stub meander-line resonator in the 0.13-µm BiCMOS technology for a 18-GHz band oscillator

In this paper, an 18 GHz voltage-controlled oscillator (VCO) with improved phase noise (PN) and smaller size is proposed. The filter consists of an open stub resonator and an integrated spiral Defective Ground Structure (DGS) resonator. The proposed oscillator is designed in the 0.13-µm SiGe BiCMOS technology. The differential cross-coupled VCO uses a bandpass filter. In this work, the conventional large-size coil is replaced by a resonator based on our proposed open stub resonator and defected ground structure (DGS) where the filter is equivalent to the large coil and the associated capacitors. The use of the filter results in a great reduction of VCO size, low losses, and low power consumption, hence an enhancement in the quality factor. The integrated spiral DGS is etched on the third metal layer (M3) below an open stub meander line onthe top metal layer (TM2) of the 0.13-µm top metal two (TM2) BiCMOS technology. The proposed VCO has a small die area of 0.089 mm2 and has FoMA of 188.8 dB and a power consumption is 13.38 mw. The simulated carrier frequency and phase noise are 18-GHz and −123.59 dBc/Hz (−103.7 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively, which results in a figure of merit of 177.37 dB.

An 18–19.2 GHz Voltage-Controlled Oscillator with a Compact Varactor-Only Capacitor Array

This paper presents a K-band CMOS cross-coupled pair voltage-controlled oscillator (VCO) that utilizes the varactor-only capacitor network. The proposed circuit features low parasitics and a compact capacitor network, such that the varactor in the analog tuning path directly affects the oscillation frequency with a large gain of the VCO, and the varactor in the digital tuning path results in minimal noise sources, thus achieving low phase noise for the automotive FMCW radar application. This VCO was designed using TSMC 65 nm technology, and the post-layout simulation results show a stable oscillation across 18–19.2 GHz, a minimum phase noise of −105.9 and −128 dBc/Hz at 1- and 10-MHz offset frequencies while dissipating 21 mW of power from a 1 V supply. Furthermore, no notable variations in phase noise are observed across the oscillation frequency tuning range. It reveals a figure of merit (FOM) of −178.3 dBc/Hz while using a varactor-only capacitor array and occupying a small chip area.

A 0.3 THz VCO using gm‐enhanced technology in 55 nm CMOS

AbstractA power combined terahertz (THz) voltage‐controlled oscillator (VCO) is proposed to increase the output power. Based on the traditional transformer‐feedback structure, a new negative conductance enhanced (gm‐enhanced) technology is presented to enhance the start‐up of the proposed THz VCO by adding additional transistors to offset the loss of the source inductance. In addition, a short transmission line is used as a zero‐phase shifter to lock the three single‐core VCOs for consistent frequency, phase, and amplitude. The fully integrated 300 GHz VCO design is fabricated in 55‐nm complementary metal oxide semiconductor (CMOS) process. The measurement results show that by modulating the bias voltage of the transistors, the VCO can achieve a tuning range of 301.2–304.2 GHz with a maximum output power of −7.5 dBm. The chip area is only 554 μm × 530 μm.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver

A clock recovery circuit for a full-rate 40 Gb/s optical receiver is presented. The proposed circuit consists of a frequency doubling block, a mixer-based phase detector, and a 40 GHz voltage-controlled oscillator. The frequency doubling block, consisting of a tuned amplifier and a frequency doubler, adopts the LC-resonator loads, rather than the conventional resistive loads, which realizes operation at 40 GHz clock frequency. The circuit is fabricated in 0.13-μm CMOS technology. Measurement results indicate that the proposed circuit is able to recover a 40 GHz clock. The recovered clock frequency is at least 1.4 times higher than other competing circuits.

저전력 77 ㎓ 전압제어발진기 설계

저전력 77 ㎓ 전압제어발진기 설계

Design of a High Temperature 2.37 GHz Voltage-Controlled Oscillator With GaN-on-SiC HEMTs

This paper presents a high temperature voltage-controlled oscillator (VCO) for downhole communications. The VCO with the center frequency of 2.37 GHz is prototyped with 0.25μm GaN-on-SiC technology high electron mobility transistors (HEMTs) and microstrip transmission lines on Rogers 4003C PCB. The measured operating temperature of the VCO ranges from 25 °C to 225 °C. A minimum tuning range of 66 MHz and less than 20% variation for the output power of 17 dBm are achieved at 225 °C. The frequency variation remains below 1.5% over the temperature range of 25 °C to 225 °C, and the harmonics power level is 20 dB lower than the fundamental. A phase noise of -131 dBc/Hz at 1 MHz offset frequency is achieved at 225 °C.

A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 $\mu$ m SiGe BiCMOS

This article presents a 9.9–12.45 GHz voltage-controlled oscillator (VCO) designed in 0.12 $\mu \text{m}$ SiGe BiCMOS with a focus on achieving the lowest possible phase noise using only a single core and maintaining the recommended Vdd of the technology. The oscillator consists of a cross-coupled design utilizing a transformer-coupled resonant tank, which takes advantage of tank parasitics to create harmonic resonances. An analysis is offered, which justifies the use of the transformer tank, noting its importance in mitigating the practical limits imposed during layout on equivalent $LC$ tanks. An excellent phase noise of −122 dBc/Hz is measured at 1 MHz offset from the carrier resulting in a figure of merit (FoM) and tuning FoM (FoMT) of −183 and −190 dBc/Hz, respectively. The VCO is incorporated into a type-II charge-pump-based phase-locked loop (PLL) with intent to be used as the local oscillator (LO) generation in a potential fifth-generation (5G) communication system.

Low-Power, Low-Phase-Noise Gm-Boosted 10-GHz VCO With Center-Tap Transformer and Stacked Transistor

This brief presents a low-power-consuming and low-phase-noise 10 GHz voltage-controlled oscillator (VCO) using the 65 nm CMOS technology. We propose a new structure for the VCO using a center-tap transformer and stacked transistor, which realizes negative $g_{m}$ -boosting to improve the phase noise and start-up conditions. The measured output frequency range of the designed VCO with a binary-weighted 3 bit capacitor bank is 9.66 to 11.07 GHz. The proposed VCO demonstrates a measured phase noise of −115.4 dBc/Hz at a 1 MHz offset frequency. To the best of our knowledge, compared to previously reported 10 GHz VCOs, the proposed circuit achieves the lowest phase noise. The proposed VCO achieves a power consumption of 2.7 mW, which reveals figure of merit and figure of merit with frequency tuning values as low as −191.4 and −194.1 dBc/Hz, respectively, and also the lowest value among state-of-the-art 10 GHz VCOs.

A 190 GHz VCO with Transformer-Based Push–Push Frequency Doubler in 40 nm CMOS

A 190 GHz voltage-controlled oscillator (VCO) with transformer-based push–push frequency doubler in 40 nm CMOS is presented. The layout optimization reduces the parasitics of the transistors. To achieve high output power at a target operating frequency of 190 GHz, design considerations are discussed and a transformer-based push–push frequency doubler is introduced. The digital controlled artificial dielectric transmission line is proposed in replacement of switched-capacitor arrays whose capacitance is more susceptible to process variation. The presented circuit occupies 390 × 430 µm2 die area including the pads and consumes 57.6 mW DC power from a 0.9 V power supply. The proposed VCO achieves a measured continuous tuning range from 181.9 to 195.5 GHz. The measured output power at 195.5 GHz is − 7.26 dBm which is estimated with the typical conversion loss of harmonic mixer. The measured phase noise at 10 MHz offset is − 97.18 dBc/Hz.

A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS

ABSTRACTThis paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of −188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2.

A Low Phase Noise 4.596GHz VCO for Chip-scale Cesium Atomic Clocks

The chip-scale cesium atomic clock can provide various devices a high accuracy and high stability frequency reference. According to its operating mechanism, a 4.596GHz voltage-controlled oscillator (VCO) with small volume, low power consumption and low phase noise is vital, serving as a microwave signal source to achieve the closed-loop clocking of the whole system. Based on this, an applicative 4.596GHz VCO is designed by using a coaxial resonator with high quality factor. Firstly, the Short-Open-Line-Thru (SOLT) calibration standards for the network analyzer are designed to extract the parameters of the used coaxial resonator and its equivalent circuit model is built. Secondly, the VCO is designed with the modified Clapp circuit topology and then the transient simulation and the harmonic balance simulation are both run to evaluate the oscillation frequency and the phase noise performance of the designed VCO. Finally, the VCO is tested and the test results show that the phase noises are -44.66dBc/Hz@300Hz and -61.12dBc/Hz@1KHz, the output power is 0.006dBm and the voltage-controlled tuning sensitivity is about 50MHz/V, well meeting the application requirements of the chip-scale cesium atomic clocks.

A 2-15 GHz VCO With Harmonic Cancellation for Wide-Band Systems

A 2-15 GHz SiGe VCO (voltage controlled oscillator) has been developed with a very low harmonic content. The design is based on the harmonic cancellation concept and uses a multiple-phase ring oscillator together with a wide-band active-weighted summer. The VCO results in an output power of −8 to −6 dBm and $3^{rd}$ and $5^{th}$ harmonic level at 2-15 GHz. The active area of the chip is very small ( $0.67 \times 0.25$ mm2) due to the lack of inductors, and the power consumption is 88-120 mW from a 2.5 V supply. To our knowledge, this is the first demonstration of a wide-band VCO showing a near-perfect sinewave output over a wide frequency range. The application areas are in built-in-self-test sources for wide-band radios and phased arrays.

주파수 잠금회로를 이용한 발진기의 위상잡음 개선

본 논문에서는 주파수 잠금회로(FLL: Frequency Locked Loop)를 이용하여 발진기의 위상잡음을 개선할 수 있음을 보였다. 1차적으로 헤어-핀 공진기를 이용하여 전압제어발진기(VCO)를 제작하였다. 제작된 VCO는 발진주파수 5 GHz에서 위상잡음을 측정한 결과, 1 kHz offset 주파수에서 -53.1 dBc/Hz를 보였다. 위상잡음을 개선하기 위하여, VCO에 5 GHz 공진기로 구성된 주파수 검출기(frequency detector), 루프 필터, 전위변환기(level shifter)를 이용 궤환회로를 구성, 주파수 잠금회로를 구성하였다. 제작된 주파수 잠금회로는 5 GHz의 주파수에서 발진하고, 1 kHz offset 주파수에서 -120.6 dBc/Hz의 위상잡음을 보였다. 따라서 주파수 잠금회로를 이용, VCO의 위상잡음을 획기적으로 약 67.5 dB 개선할 수 있음을 보였다. 또한, 얻어진 주파수 잠금회로를 이용한 발진기의 위상잡음 성능은 수정발진기의 위상잡음과 비견할만한 것이다. In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

Design of a Low Phase Noise VCO for Rubidium Atomic Frequency Standard

Compared to the size and the power consumption of the traditional atomic clocks, the ones based on coherent population trapping (CPT) can provide improvement by two orders of magnitude in both aspects above, making them needed urgently in many fields. Among different CPT atomic clocks, the one made with the rubidium atom are used widely, and their operating performance largely depends on its internal voltage-controlled oscillator (VCO) which is used to provide a proper microwave signal. Based on this, a small size and low phase noise 3.035GHz VCO is designed with a modified Clapp circuit topology using low-cost surface-mount components, including a coaxial resonant (COAX) with high quality factor. The designed VCO is simulated and optimized with the combined use of the negative resistance analysis method and the transmission analysis with a virtual-ground. In order to obtain the desired results, different values of key capacitor elements are tried according to their concrete influences on the VCO during the process of the circuit tuning. The test results show that the phase noises of the VCO are -60.49dBc/Hz@300Hz, -73.08dBc/Hz@1KHz and -97.48dBc/Hz@10KHz, the output power is -1.13dBm and the voltage-controlled tuning sensitivity is about 12MHz/V.

A 60 GHz CMOS VCO Using a Fourth-Order Resonator

In this letter, a 60 GHz voltage-controlled oscillator (VCO) implemented in the 90 nm CMOS process is presented. By using a fourth-order $LC$ resonator, the proposed VCO oscillates at its second pole frequency to achieve high speed operation with fully differential output phases and a wide tuning range with a larger size of varactors. The measured oscillation frequencies of the proposed VCO are from 58.76 to 63.94 GHz corresponding to an 8.44% tuning range. The measured phase noise is $-$ 91.53 dBc/Hz at 1 MHz frequency offset for the highest output frequency. The core circuit consumes 7.2 mW power from a 1.2 V dc supply.

Design and Analysis of 239 GHz CMOS Push-Push Transformer-Based VCO With High Efficiency and Wide Tuning Range

A push-push transformer-based voltage-controlled oscillator (VCO) is proposed and analyzed to achieve high efficiency and a wide tuning range at sub-terahertz (THz) frequencies. Analyses show that the coupling factor of the transformer to obtain high output power (POUT) has to be carefully chosen by consideration of gate-to-drain voltage gain as well as matching impedances seen from the drain and to the gate of a VCO transistor at the 2nd harmonic frequency (2fo). Analysis also shows that the transformer-based resonator allows a wide tuning range. In addition, it has been shown that the introduction of a parallel inductor to a varactor leads to high POUT and low phase noise. The proposed 239 GHz VCO with a 65 nm CMOS process demonstrates the high efficiency of 1.45%, the POUT of -4.8 dBm, and the wide tuning range of 12.5% with a supply voltage of 1.2 V.

Buckled diamond-like carbon nanomechanical resonators.

We have developed capacitively-transduced nanomechanical resonators using sp(2)-rich diamond-like carbon (DLC) thin films as conducting membranes. The electrically conducting DLC films were grown by physical vapor deposition at a temperature of 500 °C. Characterizing the resonant response, we find a larger than expected frequency tuning that we attribute to the membrane being buckled upwards, away from the bottom electrode. The possibility of using buckled resonators to increase frequency tuning can be of advantage in rf applications such as tunable GHz filters and voltage-controlled oscillators.

21.5-to-33.4 GHz Voltage-Controlled Oscillator Using NMOS Switched Inductors in CMOS

To demonstrate the applicability of NMOS switched variable inductors in the millimeter wave frequencies, a 21.5 to 33.4 GHz wide tuning range LC voltage-controlled oscillator (LC-VCO) with frequency tunable output buffers that uses variable inductors is reported. The measured phase noise at 10 MHz offset of VCO fabricated in a 65 nm bulk CMOS process varies from -117 to -109 dBc/Hz. The oscillator core consumes 4 or 6 mA from a 1.2 V power supply. These correspond to a record 43.3% tuning range. FOMT ranges from -191.7 to -181.9 dBc/Hz. With tunable output buffers, the measured signal output power is above -15 dBm across the entire frequencies.