GHz PA Research Articles

Design and Electromigration Study for a Stacked Distributed Power Amplifier

In this paper, the implementation and electro-migration (EM) study in GaAs pHEMT stacked distributed power amplifier (SDPA) is presented. A 0.2[Formula: see text]7 GHz PA is designed using a 0.15[Formula: see text][Formula: see text]m GaAs pHEMT process, which employs 4-distributed 2-stacked-field effect transistors (FETs) to obtain about 1-watt output power with corresponding power added efficiency (PAE) of 26–32% within a very small chip size of 2.9[Formula: see text]mm2. Using the finite element analysis (FEA), the EM prediction for an SDPA is achieved effectively to find the weakest spot for the stacked distributed PA. This can provide valuable guidance for circuit design and analysis.

Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs

This paper presents a simple but accurate normalized nonlinear large-signal semiempirical MOS transistor model to be used in monolithic RF Class A-to-C PAs. MOS transistor characteristics, saved in lookup tables, are extracted for different PVT corners, allowing the study of the PA performance spread. Model accuracy is ratified by the excellent matching obtained when comparing data algebraically calculated with electrical simulations of hundreds of PAs, and with the measurement data of a fabricated 2.4 GHz PA.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

A fully-integrated reconfigurable dual-band (760–960 MHz and 2.4–2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by ×3.24 and ×1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by ×2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.

On a Design of 5GHz Linear Power Amplifier with MOS Process

In recent years, RF power amplifiers in MOS process are designed. In this paper, we discuss design considerations for MOS RF linear power amplifier. At first, we analyze class-A and AB amplifiers based on square-low characteristics and derive their distortion and drain efficiency, which include different results from literatures. We then consider a class-A 5GHz PA design with push-pull and Series-Combining Transformer configuration in 90nm process. Simulation results show that linear output up to 20.1[dBm] and P1dB of 21[dBm] are obtained.