GHz LC-VCO Research Articles

Design of a 1.29–1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation

This paper demonstrates a low-phase noise and high FoMT differential CMOS LC-VCO working at 1.29–1.61[Formula: see text]GHz. An RC filter tail current source is used in this design to reduce the second-harmonic oscillation phase noise. The VCO is implemented in 180[Formula: see text]nm process technology. The post-layout simulation results indicate that this proposed VCO operates faithfully in the 1.29–1.61[Formula: see text]GHz band with a frequency tuning range (FTR) of 320[Formula: see text]MHz. By using inversion mode N-MOSFET varactor, the designed VCO obtains 22.06% FTR. The phase noise of the VCO is [Formula: see text]130.21[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency. It consumes 4.01[Formula: see text]mW average power from 1.3[Formula: see text]V supply. The cell area occupied by the design is [Formula: see text]. Figure-of-merit considering FTR (FoM[Formula: see text] is [Formula: see text]194.14[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency, phase noise and average power consumption. The proposed VCO can be used for low-phase noise GPS and satellite navigation.

A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO

Varactors in RF CMOS processes often have significantly lower Q- factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{VAR}$ </tex-math></inline-formula> ) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{T} &lt; Q_{VAR}$ </tex-math></inline-formula> , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{T}$ </tex-math></inline-formula> . The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{VAR}$ </tex-math></inline-formula> . Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula> of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula> of −194.2 dBc/Hz.

A Low Power, Low Phase Noise, 11.8 GHz LC-VCO in 65 nm CMOS for 5G NR Based C-V2X Applications

An 11.8-GHz low-power, low phase noise, 65-nm CMOS LC-VCO for V2X communication standards is presented in this work. To achieve low-phase noise performance to fulfill the 5G NR C-V2X standards, several adjustments are made to the conventional LC-VCO topologies. These adjustments are briefly explained in this work. Presented VCO consumes 3.046[Formula: see text]mA current from a 1.2-V power supply. It has [Formula: see text]116.13[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset and tuning range between 11.64[Formula: see text]GHz and 11.94[Formula: see text]GHz. A frequency divider circuit is designed and implemented to the presented VCO to satisfy the frequency spectrum of V2X radio access technologies. To the best of authors’ knowledge, this work is the first VCO implemented at 11.8 GHz in a 65-nm CMOS process with the reported phase noise number for 5G NR C-V2X applications.

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

A Novel Approach for Low Phase Noise Voltage Controlled Oscillator Design based on TSMC 0.18 um Technology

In this paper, a new structure of Voltage Control Oscillator (VCO) to reduce the phase noise using two plans of a variable voltage capacitor is proposed. The aim of the current paper is to analyse two structure of a completely integrated 3.7 GHz LC-VCO based on TSMC 0.18 um technology. In the first plan for different voltages with variable voltage capacitors in this circuit can be achieved to a suitable phase noise of about 125 dB per Hz and in the second plan, a noise of -123 dB per Hz is achieved in the deviation frequency of 1 MHz. Also, the Figure of Merit (FOM) values for the first plan of -4/186 and for the second plan of –4/184 are achieved and the power consumption is 10 mW.

Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range

In this paper, a 2 GHz LC-VCO with neural network (Multilayer Perceptron) has been designed in a 0.13 ţm CMOS technology. With the integrated neural network, the linearity and tuning range of the LC-VCO has been substantially improved. Compared to a conventional VCO design, the proposed technique can improve the linearity by selecting optimized bias voltages obtained from the output of the neuron network. The result shows that the tuning nonlinearity of the proposed VCO is further optimized from 0.335% to 0.254%.

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2 $$\omega _0$$ . The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 $$\upmu$$ W from 400 mV dc supply. This VCO achieves a phase noise of $$-\,122.3$$ and $$-\,111.7$$ dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is $$-\,199.7$$ and $$-\,192.4$$ dBc/Hz, respectively. And it is under $$-\,190.5$$ dBc/Hz through all the tuning range. The FoM $$_T$$ at 1 MHz offset from 5.17 GHz carrier is $$-\,210.6$$ dBc/Hz. The proposed design was simulated for three different temperatures ( $$-\,55$$ , 27, $$125\,^{\circ }\hbox {C}$$ ), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.

A mm-Wave CMOS LC-VCO With Vertically-Coiled Solenoid Inductor

This letter presents a small area mm-wave CMOS LC-VCO with vertically-coiled solenoid inductor. Based on the multi-layers of metals and the vias among them in CMOS process, vertically-coiled solenoid inductor with small area is formed with the inductance at the order of hundred pHs. An accurate compact model for the vertically-coiled solenoid inductor over a broad frequency range has been developed, the method to analytically extract the model parameters is also presented in details. A 24 GHz LC-VCO with the vertically-coiled solenoid inductor was implemented in 90 nm CMOS process. It occupies a core area of 250 $\mu\text{m}$ $\times$ 85 $\mu\text{m}$ , the measured phase noise is $-$ 122 dBc/Hz@10 MHz when the output frequency is 23.6 GHz.

Design of SET tolerant LC oscillators using distributed bias circuitry

In this paper, a distributed biasing technique is proposed to improve the single event transient (SET) tolerance in LC-tank voltage controlled oscillators. The charge generated by a radiation strike at the drain of the bias current transistor results in voltage change at the drain node, which causes change in the output impedance of the transistor. This effect is more pronounced in the case of distributed biasing, and is used for improving the SET tolerance in the oscillator. Circuit simulations show that the phase error introduced due to a radiation strike is reduced to one-third in a 14GHz LC–VCO designed in a standard 90nm CMOS technology when the distributed bias is used, as compared to the phase error in a conventional LC–VCO.

A power scalable PLL frequency synthesizer for high-speed Δ—Σ ADC

A 35–130 MHz/300–360 MHz phase-locked loop frequency synthesizer for Δ—Σ analog-to-digital converter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300–360 MHz) or in low-power mode (35–130 MHz) to satisfy the ADC's requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of −132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of −112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048×1.076mm2 is fabricated in a TSMC 0.18μm CMOS 1P6M technology process.

A Wideband 9 GHz LC-VCO with Tail Current Source Array in 0.18-μm RF CMOS Process

A wideband 9 GHz LC-VCO with tail current source array based on TSMC 0.18-μm RF CMOS process is presented in this paper. After discussing the start-up conditions, the structure of tail current source array is utilized to lower the power consumption in high frequency bands and guarantee start-up at low frequency bands. Furthermore, to extend the frequency range, a 4-bit switched capacitor array is used. Based on our analysis, a NMOS cross-coupled VCO with 4-bit PMOS tail current source array is implemented. Post-simulation results show that the tuning range is from 6.372GHz to 9.154GHz and the phase noise at 1MHz offset is less than-110dBc/Hz in the entire tuning range. The operating current of the VCO core is from 8.24mA to 13.362mA in the entire tuning range under 1.8V supply voltage. And the area of the proposed VCO is 1177.775μm × 577.54μm, with two buffer stages and pads.

A 20–40 MHz low-power clock oscillator with open-loop frequency calibration and temperature compensation

In this paper, a 20–40 MHz low-power clock oscillator is presented to provide the frequency reference in data interface applications. The frequency source is referenced to a frequency-calibrated and temperature-compensated 2.5 GHz LC VCO that is implemented with a bondwire inductor. Class-C type VCO is adopted in order to improve the phase noise and reduce the current consumption. A full digital frequency calibration circuit is proposed to cover the wide output frequency range minimizing the frequency variation. External crystal oscillator (REF_CLK) is used only for the absolute frequency calibration at the initial programming stage and is not needed after the programming stage. On the other hand, temperature compensation is performed in an analogue way by controlling the varactor in the LC VCO. This chip is fabricated using 0.18-µm CMOS with the option of lateral PNP transistor. Lateral PNP transistors are used in the temperature compensation circuits. It can be implemented laterally in standard CMOS process. The power consumption is 4.8 mW from a 1.8 V supply. The accuracy of the frequency is ±58 ppm from −20°C to 80°C. The nominal phase noise at 1 MHz and period jitter is −122 dBc/Hz and 2 ps, respectively, when the output frequency is 25 MHz.

An ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology

This paper presents an ultra low power consumption 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65 nm CMOS SOI process, which improves passive devices behavior. The proposed VCO achieves a frequency tuning range (FTR) of 9.7 % and a phase noise of ?110.86 dBc/Hz at 10 MHz of the carrier. All integrated passive components (including transmission lines and a transformer-based balun) are modeled using advanced electromagnetic (EM) field solvers. The power consumption of the proposed VCO is as low as 1.1 mW when biased by a 0.8-V supply voltage. The FoM of this millimeter wave circuit, whose core occupies a silicon footprint of only 0.047 mm2, is ?184.07 dBc/Hz.

Low phase noise LC VCO with reduced drain current duty cycle

A novel LC VCO topology with switched current source is presented. Theoretical analysis is given to show the reduction of cross-paired transistors' drain current duty cycle with the implementation of current source switching, which reduces the upconversion of 1/f noise and also provides noise shaping by directly reducing 1/f noise. A 5.25'5.5 GHz LC VCO has been fabricated and measured for the proposed topology, achieving a FOM of '191 dBc/Hz, which is among the best published FOM results for 5'6 GHz VCOs in standard CMOS process.

14.6–22.2 GHz LC-VCO in 65 nm CMOS technology for wideband applications

For ultra-wideband RF systems, a wide frequency tuning range of an LC-VCO is highly desired. Presented is an LC-VCO operating at 20 GHz with differentially tuned MOS varactors. A simple voltage converter is used to generate the differential tuning voltages without compromising the VCO gain or phase noise. When implemented in 65 nm CMOS technology, the VCO achieves 14.6-22.2 GHz tuning range and exhibits a worst-case phase noise of -96 dBc/sqrt(Hz) at 1 MHz offset across the entire frequency range. The VCO core consumes 4 mA of current from a 0.65 V supply and occupies approximately an area of about 0.06 mm 2 .

A 0.06 mm$^{2}$ 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS

GSM-compliant local oscillator consuming a tiny die area of only 0.06 mm and drawing 9 mA from a 1.2 V supply has been designed in a 65 nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the divider is below -133 dBc/Hz at 3 MHz offset over the tuning range.

Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5–7 GHz $LC$-VCO

The coupling of the transmitted radio-frequency (RF) signal of the power amplifier (PA) in the sensitive voltage-controlled oscillator (VCO) remains a major problem for system-on-chip (SoC) design. Coupling between these two circuits may cause malfunctioning of the system. This paper analyzes the different coupling mechanisms between a 4 GHz prepower amplifier (PPA) and a 5-7 GHz LC-VCO designed in 0.13 mum technology. Different experiments are carried out to reveal the dominant coupling mechanisms. Insight into these mechanisms leads to the proposal of proper countermeasures.

A 23‐GHz capacitive‐degeneration LC VCO with a FOM of −199 dBc/Hz

AbstractIn this article, we presents a fully differential 23‐GHz capacitively emitter‐degeneration double cross‐coupled LC‐tank VCO. The proposed capacitive‐degeneration negative‐resistance cell has higher ftrans and lower input capacitance than conventional cross‐coupled pairs at millimeter‐wave band. The proposed capacitive‐degeneration LC VCO shows low phase noise of −105 dBc/Hz at 100 kHz offset from 23 GHz carrier and wide tuning range of 20.8–24.2 GHz, and consumes 10 mA current. The proposed 23 GHz LC VCO shows a good FOM of −199 dBc/Hz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1688–1690, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23453