GHz fractional-N Frequency Synthesizer Research Articles

0.18-μm CMOS process 40 MHz–4.41 GHz frequency synthesizer with high linearity low phase noise varactor-reconstruction LC-VCO

A 40 MHz–4.41 GHz fractional-N frequency synthesizer (FS) with varactor-reconstruction VCO (VRVCO) fabricated in the standard 0.18-μm CMOS process is demonstrated. In the conventional VCO, owing to non-linearity of varactor and parasitic effects of switched-MOSFET, the top and bottom of the tuning curves show nonlinearity. The novel design of VRVCO for tuning sensitivity base on series-shunt hybrid capacitor-varactor part and optimized switched-capacitor bank is incorporated into the 4.41 GHz FS design to reduce the variation of the VCO gain, realize high linearity tuning curves and improve phase noise performance. Furthermore, a noise reduction topology is adopted to decrease phase noise of VRVCO. Simulated results show the proposed VRVCO can improve linearity of tuning frequency over the entire tuning range. The measured results show the overall tuning range exceeds 115% from 1.92 to 4.41 GHz including three VRVCOs with high linearity (fine-tuning sensitivity: 131%, coarse-tuning sensitivity: 106%) and the phase noise is −120dBc/Hz at 1 MHz offset from the carrier frequency of 4.41 GHz.

An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios

This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used for wideband operation. Second harmonic filtering and high frequency noise suppression techniques are applied in VCO for phase noise optimization. Inverter switch and cascade switch buffers are combined for channel selection enhancement and output amplitude improvement. A large output voltage dynamic range with minimum current variation and mismatch is achieved by enabling transistors to work in triode region in charge pump. Implemented in a 55 nm CMOS process, the synthesizer demonstrates continuous frequency coverage from 62.5 to 4000 MHz with orthogonal output signals greater than 2 dBm while consuming 125 mW of power and provides the phase noise performance of −96.3/-127.7 dBc/Hz at 10 kHz/1 MHz offsets under a 2 GHz carrier. The chip area including all the pads and IOs is 3.34 mm2.

A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect

An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect

A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 1.78–3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4 GHz broadband fractional-N frequency synthesizer based on Σ---Δ modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The "mod" signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18 μm RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05 GHz, with phase noise smaller than ?85 dBc/Hz at 100 kHz offset, and smaller than ?115 dBc/Hz at 3 MHz offset. Its power consumption is only 9.2 mW under 1.8 V supply voltage, and the chip occupies an area of 1.2 mm × 1.3 mm.

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18 μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order Σ–Δ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8o respectively. The measured phase noise is −116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than −60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.

A 1.8- GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.