Geometric Programming Framework Research Articles

Millimeter Wave and Free-space-optics for Future Dual-connectivity 6DOF Mobile Multi-user VR Streaming

Dual-connectivity streaming is a key enabler of next-generation six Degrees Of Freedom (6DOF) Virtual Reality (VR) scene immersion. Indeed, using conventional sub-6 GHz WiFi only allows to reliably stream a low-quality baseline representation of the VR content, while emerging high-frequency communication technologies allow to stream in parallel a high-quality user viewport-specific enhancement representation that synergistically integrates with the baseline representation to deliver high-quality VR immersion. We investigate holistically as part of an entire future VR streaming system two such candidate emerging technologies, Free Space Optics (FSO) and millimeter-Wave (mmWave), that benefit from a large available spectrum to deliver unprecedented data rates. We analytically characterize the key components of the envisioned dual-connectivity 6DOF VR streaming system that integrates in addition edge computing and scalable 360° video tiling, and we formulate an optimization problem to maximize the immersion fidelity delivered by the system, given the WiFi and mmWave/FSO link rates, and the computing capabilities of the edge server and the users’ VR headsets. This optimization problem is mixed integer programming of high complexity and we formulate a geometric programming framework to compute the optimal solution at low complexity. We carry out simulation experiments to assess the performance of the proposed system using actual 6DOF navigation traces from multiple mobile VR users that we collected. Our results demonstrate that our system considerably advances the traditional state of the art and enables streaming of 8K-120 frames-per-second (fps) 6DOF content at high fidelity.

Resource Allocation in Topology Management of Asymmetric Interference Networks

Most existing works of interference alignment focus on symmetric networks. When the difference of path loss is considered in asymmetric networks, topology management needs to be carefully designed for interference-alignment-based interference networks. Using topology management, the network is separated into an interference alignment subnetwork and some spatial multiplexing subnetworks. In this paper, antenna selection and power allocation techniques are exploited to further improve the performance of topology management in asymmetric interference networks. First, the antenna selection technique is applied to interference alignment subnetworks. Through fully utilizing the redundant antennas, more optional antenna combinations can be provided to achieve the diversity gain. Then, based on the geometric programming framework, the transmitted power is allocated among transmitters of both the interference alignment and spatial multiplexing subnetworks, to optimize the spectrum efficiency of the network. Based on these two techniques for the topology management scheme, the joint optimization of antenna selection and power allocation is developed through a stepped resource allocation optimization strategy to further improve the performance with low computational complexity. Simulation results are presented to show the effectiveness of the proposed algorithms.

Analytical performance model for FPGA-based reconfigurable computing

Traditionally, FPGA designers make use of CAD tools for evaluating architectures in terms of the area, delay and power. Recently, analytical methods have been proposed to optimize the architectures faster and easier. A complete analytical power, area and delay model have received little attention to date. In addition, previous works use analytical methods to optimize general-purpose FPGA architectures. Using analytical models for optimizing application-specific FPGA architectures are interesting subjects in the reconfigurable computing field. In this way, designers can investigate the optimized architecture for a set of application circuits and the consumers can find their best architecture among a variety of devices which is optimal for their specific work. In this paper, we complete an analytical FPGA performance model by presenting an analytical model to estimate the dynamic and leakage power and by integrating it into the geometric programming framework. This way, we are able to rapidly analyze various FPGA architectures and select the best one in terms of power consumption as well as area and delay. In the next step, we extend the model for optimizing FPGA architectures for a set of applications. A case of the best architecture for two specific circuits has been investigated in this paper.

Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming

paper presents the application of geometric programming for combined high-level and low-level architecture parameter exploration. This paper builds an geometric programming framework for reconfigurable architectures, and presents a full delay and area model of an FPGA. This optimization allows high-level architectural parameter selection and the transistor sizing to be done concurrently. The transistor values are derived using 45nm predictive technology model. CVX framework for MATLAB is used to run the geometric programming framework. The area and critical path delay are determined for given cost function by single-stage and multi- stage approach.

Joint source and relay power allocation in amplify-and-forward relay networks: a unified geometric programming framework

This study presents some joint source and relay power allocation algorithms in the amplify-and-forward (AF) relay networks using the efficacious geometric programming (GP). According to the constraints, approximate expressions of the received signal-to-noise ratio are first obtained. Thereafter, the problems are cast into appropriate GP forms according to the constraints. The power allocated to the source(s) and to the relays is then determined iteratively via the single condensation method. The new GP approach is shown to be applicable to a variety of constraints by using all of the relays for assistance and is amenable to asymmetric channels in both the single-user and multi-user AF relay networks. Conducted simulations show that the proposed power allocation schemes can attain superior performance compared with the previous works under various constraints in miscellaneous scenarios.

FPGA Architecture Optimization Using Geometric Programming

This paper is concerned with the application of geometric programming to the design of homogeneous field programmable gate array (FPGA) architectures. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. We use a geometric programming framework to show how transistor sizing and high-level architecture parameter selection can now be solved as a concurrent optimization problem. We validate the model through the use of simulation program with integrated circuit emphasis (SPICE) models and the versatile place and route (VPR) FPGA architecture simulation tool. Not only does the optimization framework allow architectures to be optimized orders of magnitude faster than previous work, but the combined optimization can lead to different architectural conclusions compared to conventional methods by exploring the coupling between the two sets of optimization variables. Specifically, we show that as delay takes more significance in the objective of the optimization, there should be more lookup tables in a logic block, whereas conventional techniques suggest that there should be fewer lookup tables in an FPGA logic block.

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geometric</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">programming</i> problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times.

A Geometric Programming Framework for Univariate Cubic L 1 Smoothing Splines

Univariate cubic L1 smoothing splines are capable of providing shape-preserving C1-smooth approximation of multi-scale data. The minimization principle for univariate cubic L1 smoothing splines results in a nondifferentiable convex optimization problem that, for theoretical treatment and algorithm design, can be formulated as a generalized geometric program. In this framework, a geometric dual with a linear objective function over a convex feasible domain is derived, and a linear system for dual to primal conversion is established. Numerical examples are given to illustrate this approach. Sensitivity analysis for data with uncertainty is presented.