The Key Objective is HDL RTL Design Architecture of Ultra high multi Clock Frequency Speed Rate ( MHz, GHz, THz, PHz, EHz, ZHz, etc) Bits Per Second Baud Rate ) P.R.B.S(Pseudo Random Binary Sequence) Transceiver Soft A.S.I.C IP Core product for identification of the property of Different Pseudo Random Binary Sequence Patterns (Seed Words) of 2e 7 -1, 2e10 -1, 2e 15 -1, 2e 23 -1, 2e 31 -1 tapped elements as per C.C.I.T.T-I.T.U Standards and IEEE-754 Single and Double Data Rate Data Precision Standards (32 bit & 64 Bit Data Width ) suited for Very Advanced Futuristic Hi-tech Smart High Speed Long Distance Wireless Digital Communication A.S.I.C Products / Applications like Space/Satellite, Aerospace and Large Data Processing and computing like High Speed Internet and Cloud Computing based Hi-Fi Industrial Data Automation Standard Ultra High Speed Wireless Communication A.S.I.C products and Applications-3G,4G,5G etc. The Multi channel PRBS Transceiver consists Transmitter and receiver of different PRBS patterns- 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ. The data input transmitted and received serially in the form bit by bit. These different pattern sequences are Designated as per CCITT ITU 0.151/O.152/O.153 & AT&T Standards. The Aim and purpose of invention of Ultra high multichannel Clock frequency PRBS Transceiver is for transmit and receive data serially by using Tx_in and Tx_out, rxin, rxout signals and The Transceiver is processed the low frequency signal input with different high speed carrier wave frequencies in the form of different PRBS pseudo random binary sequence seed word bit/byte patterns -2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ and also on receiver side processed with the above patterns. Materials and Methods: Transmission and reception of Data serially based on the Deterministic random seed word pattern methods of different PRBS 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 tapped sequence Elements and All these PRBS are purely synchronized with Ultra high clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz). The Soft IP Core Designed by System Verilog HDL/ Verilog HDL. RTL Design Simulation done by Synopsys VCS 2020.1 software and Altera Model-Sim Software and Logic Design Flow & Synthesis done by Xilinx ISE and Altera Quartus EDA Tools. Results: Generation of Simulation Display and waveform for Ultra High Clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz) Synchronized Pseudo Random Binary Sequence (PRBS) Register Transfer Level (RTL) Generators, Transceiver for efficient and effective High Quality Data transmission and Reception of Various tapped sequence patterns for Identification of property of different PRBS patterns2e7 -1, 2e10-1, 2e15-1, 2e23 -1, 2 31 -1 NRZ of Ultra high speed Long distance wireless engineering Applications/ products.