Abstract Bayesian network are crucial components for uncertainty reasoning and knowledge representation in probabilistic graphical models. As model complexity increases, traditional digital methods face challenges in efficiency and resource utilization. In this work, a novel Bayesian network optimization method based on one-transistor one-memristor (1T1M) units for storing and accessing probability values was proposed. This method leverages the sigmoid-like characteristics of 1T1M for computational optimization, integrates probability storage into sigmoid belief network (SBN), and extends to the variational autoencoder (VAE) framework. By storing and manipulating probabilities at hardware level, this approach enhances storage efficiency and access speed while enhancing computational precision and model expressiveness through the sigmoid-like space of 1T1M. Validation experiments using the MNIST digit generation task demonstrate that this method exhibits unique advantages in SBN structures, particularly in handling complex conditional probabilities and inference tasks. Compared to traditional digital implementations, the proposed method exhibits potential advantages in inference speed and hardware utilization.
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