Custom Instruction Generation Research Articles

Parallel Enumeration of Custom Instructions Based on Multidepth Graph Partitioning

Automatic generation of custom instructions is the key to the extensible processors. The generation of custom instructions includes two crucial steps: 1) custom instruction enumeration and 2) custom instruction selection. This letter focuses on the custom instruction enumeration step. Enumerating all custom instruction candidates satisfying architectural constraints from an application graph is a computationally difficult problem. Considering the high complexity of the custom instruction enumeration, we propose a simple but efficient parallel search method based on multidepth graph partitioning for enumerating custom instructions. Experimental results show that the proposed method can give near-linear speedup and outperforms the latest parallel methods.

FPGA-aware techniques for rapid generation of profitable custom instructions

Instruction set extension of FPGA based reconfigurable processors provides an effective means to meet the increasingly strict design constraints of embedded systems. We have shown in our previous works [20,21] that the usage of FPGA architectural constraints for pruning the design space during enumeration of custom instructions/patterns not only leads to notable reduction in the time taken to identify custom instructions but can also result in the selection of profitable custom instructions when the area is highly constrained. However when area constraint is relaxed, the previously proposed methods failed to perform better than traditional methods. In this paper, we propose a heuristic to identify profitable custom instructions for designs with arbitrary area constraints. The proposed heuristic relies on a new pruning criterion to enumerate patterns with high size-to-hardware-area ratio. We also proposed a suitable algorithm to select profitable custom instructions from the enumerated patterns. The proposed template selection algorithm takes advantage of the FPGA area-time measures of the enumerated patterns, which can be easily inferred from the FPGA-aware enumeration strategy. Experimental results show that the proposed methods in this paper result in custom instructions that achieve an average performance gain of 76.23% over current state-of-the-art approaches.

Encoding Custom Instruction Generation as Satisfiability Problem

The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefore, we present in this paper a propositional satisfiability approach to efficiently identify the custom instructions which contain a large number of valid nodes. Our approach is different substantially from the previous works where it uses an edge classification method to reduce the search space for convexity checking. The experiment results show that our method can, in a matter of few seconds, identify a set of custom instructions that speed up the application to a few times faster.

Fast Generation of Multiple Custom Instructions under Area Constraints

Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands

This paper presents a novel framework to generating efficient custom instructions for common configurable processors with limited numbers of I/O ports in the register files and fixed-length instruction formats, such as RISCs. Unlike previous approaches which generate a single custom instruction from each subgraph, our approach generates a sequence of multiple custom instructions from each subgraph by applying high-level synthesis techniques such as scheduling and binding to the subgraphs. Because of this feature, our approach can provide both of the following two advantages simultaneously: (1) generation of effective custom instructions from Multiple Inputs Multiple Outputs (MIMO) subgraphs without any change in the configurable processor hardware and the instruction format, and (2) resource sharing among custom instructions. We performed synthesis, placement and routing of the automatically generated Custom Functional Units (CFUs) on an FPGA. Experimental results showed that our approach could generate custom instructions with significant speedups of 28% on average compared to a state-of-the-art framework of custom instruction generation for configurable processors with limited numbers of I/O ports in the register file and fixed-length instruction formats.

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands

Rapid generation of custom instructions using predefined dataflow structures

Custom instruction generation is fast becoming popular as it provides an alternative means to realize application specific processors. In this paper, we propose an efficient methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors) using predefined sets of dataflow structures that are based on templates and reusable structures. A novel template selection strategy was employed to reduce the number of templates required for matching by up to 50%, while providing comparable performance with known approaches. It has been shown that custom instructions could be realized through instantiation of a reduced set of pre-designed reusable structures. Experimental results show that a small number of reusable structures can sufficiently cater to custom instruction generation to notably reduce the time required to realize them on configurable hardware. Moreover, based on our evaluations using MiBench benchmark suites, the reusable structures constitute to only 2% of all the custom instruction instances. The custom instructions generated with reusable structures were implemented in FPGA and it is evident that up to 14% area savings with comparable performance can be achieved when compared with conventional implementation approaches.

Automated Custom Instruction Generation for Domain-Specific Processor Acceleration

Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or coprocessors), and the corresponding instructions are added to a baseline processor to meet the critical computational demands of a target application. In this paper, the design of a system to automate the instruction set customization process is presented. A dataflow graph design space exploration engine efficiently identifies computation subgraphs to create custom hardware and a compiler subgraph matching framework seamlessly exploits this hardware. We demonstrate the effectiveness of this system across a range of application domains and study the applicability of the custom hardware across an entire application domain. Generalization techniques are presented which enable the application-specific hardware to be more effectively used across a domain.