General Purpose Programmable Processors Research Articles

General-purpose programmable photonic processor for advanced radiofrequency applications

A general-purpose photonic processor can be built integrating a silicon photonic programmable core in a technology stack comprising an electronic monitoring and controlling layer and a software layer for resource control and programming. This processor can leverage the unique properties of photonics in terms of ultra-high bandwidth, high-speed operation, and low power consumption while operating in a complementary and synergistic way with electronic processors. These features are key in applications such as next-generation 5/6 G wireless systems where reconfigurable filtering, frequency conversion, arbitrary waveform generation, and beamforming are currently provided by microwave photonic subsystems that cannot be scaled down. Here we report the first general-purpose programmable processor with the remarkable capability to implement all the required basic functionalities of a microwave photonic system by suitable programming of its resources. The processor is fabricated in silicon photonics and incorporates the full photonic/electronic and software stack.

"Roto-Rooting" your router

Our work presents the first practical example of an entirely new class of network attacks - attacks that target the network infrastructure. Modern routers use general purpose programmable processors, and the software used for packet processing on these systems is potentially vulnerable to remote exploits. We describe a specific attack that can launch a devastating denial-of-service attack by sending just a single packet. We also show that there are effective defense techniques, based on processor monitoring, that can help in detecting and avoiding such attacks.

Securing the data path of next-generation router systems

As the technology used to implement computer network infrastructure advances, networking resources are becoming more vulnerable to attack. Recent router designs are based on general-purpose programmable processors, which increase their potential vulnerability. To address this issue, a Secure Packet Processing platform has been developed that can flexibly protect emerging router systems. Both instruction-level operation of embedded processors and I/O operations of router ports are monitored to detect anomalous behavior. If such behavior is detected, a recovery system is invoked to restore the system into an operational state. Experimental results show that processor-based attacks can generally be determined by a processing monitor within a single instruction. I/O anomalies, including unexpected packet broadcast or delay, can be detected by an I/O monitor with limited overhead. Overall, the system overhead for secure monitoring is limited to a fraction of the overall system space, memory, and power budget.

Application specific instruction-set processor template for motion estimation in video applications

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

Reconfigurable optical interconnections for parallel computing

We describe our research on optically interconnected optoelectronic parallel computing systems. Our architecture is based on a multilayer pipeline of two-dimensional optoelectronic device arrays in which each pixel is composed of an optical input channel, a general-purpose programmable processor, local memory, and a surface-emitting laser diode as an optical output channel. Free-space optics provides parallel, global communication between layers in the pipeline via optical paths that are dynamically reconfigurable. Design and initial realization of a system are described.

Optoelectronic parallel computing using optically interconnected pipelined processing arrays

We describe our research on optoelectronic parallel computing systems. Our architecture is based on a multilayer pipeline of two-dimensional optoelectronic device arrays in which each pixel is composed of an optical input channel, a general purpose programmable processor, local memory, and a surface-emitting laser diode as an optical output channel. Free-space optics provides parallel, global communication between layers in the pipeline via optical paths which are dynamically reconfigurable. Demonstration systems and some applications are described.

SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Therefore a systems perspective of the design process is essential, as opposed to the conventional "chip-focused" approach. A design framework, called SIERA, for application-specific systems is described in which higher level aspects of system design, including software, multichip design issues present at the board level, and hardware-software integration are addressed, in addition to the design of individual custom chips. A high-level description of the system as a network of processes is mapped to a system architecture template consisting of multiple boards using dedicated hardware modules and ASIC's as well as software processes running on programmable hardware modules. Application of SIERA's design methodology to a multisensory robot control system is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>