General-purpose Computer Research Articles

A prediction model for surface settlement during the construction of variable cross-section tunnels under existing structures based on stochastic medium theory

When predicting ground surface settlement caused by constructing a new tunnel beneath existing structures, traditional stochastic medium theory inadequately accounts for the effects of abrupt changes in the cross-sectional areas of variable-section tunnels and the presence of existing structures, potentially leading to significant errors. In this paper, an enhanced ground surface settlement prediction model, based on stochastic medium theory, is proposed. The model equates the settlement of the existing structure’s base slab to that of the overlying soil and divides the horseshoe-shaped tunnel cross-section into eight arc segments, which are calculated using a polar coordinate system. Furthermore, the model treats soil loss at the junctions of variable-section tunnels as a linear transition, introduces the concept of a linear transition segment for variable sections, and accounts for the superimposed effects of closely spaced twin-tunnel excavations. Based on this model, a general-purpose calculation program has been developed that enables the rapid prediction of ground surface deformation caused by a variable-section tunnel passing beneath existing structures, simply by inputting engineering parameters. Finally, the accuracy of the prediction model was validated through comparisons with field measurement data, finite element analysis results, and calculations based on traditional stochastic medium theory. The results indicate that the proposed prediction model demonstrates high consistency with field data and finite element analysis results, whereas traditional stochastic medium theory results exhibit significant errors. This model is scientifically valid and provides a reliable reference for predicting ground surface settlement in comparable variable-section metro tunnel construction projects.

Boolean Circuits in Colloidal Mixtures of ZnO and Proteinoids.

Liquid computers use incompressible fluids for computational processes. Here, we present experimental laboratory prototypes of liquid computers using colloids composed of zinc oxide (ZnO) nanoparticles and microspheres containing thermal proteins (proteinoids). The choice of proteinoids is based on their distinctive neuron-like electrical behavior and their similarity to protocells. In addition, ZnO nanoparticles are chosen for their nontrivial electrical properties. Our research demonstrates the successful extraction of 2-, 4-, and 8-bit logic functions in ZnO proteinoid colloids. Our analysis shows that each material has a distinct set of logic functions and that the complexity of the expressions is directly related to each material present in a mixture. Our study shows that 2-, 4-, and 8-bit logic functions can be successfully extracted from ZnO proteinoid colloids. These findings provide a basis for the development of future hybrid liquid devices capable of general-purpose computing.

Field theory with the Maxima computer algebra system

The Maxima computer algebra system, the open-source successor to MACSYMA, the first general-purpose computer algebra system that was initially developed at the Massachusetts Institute of Technology in the late 1960s and later distributed by the United States Department of Energy, has some remarkable capabilities, some of which are implemented in the form of add-on, “share” packages that are distributed along with the core Maxima system. One such share package is itensor, for indicial tensor manipulation. One of the more remarkable features of itensor is functional differentiation. Through this, it is possible to use itensor to develop a Lagrangian field theory and derive the corresponding field equations. In this paper, we demonstrate this capability by deriving Maxwell’s equations from the Maxwell Lagrangian, and exploring the properties of the system, including current conservation.

N-AquaRAM: A Cost-Efficient Deep Learning Accelerator for Real-Time Aquaponic Monitoring

AbstractAquaponics is an emerging area of agricultural sciences that combines aquaculture and hydroponics in a symbiotic way to increase crop production. Though it offers a lot of advantages over traditional techniques, including chemical-free and soil-less farming, its commercial application suffers from some problems such as the lack of experienced manpower. To operate a stable smart aquaponic system, it is critical to estimate the fish size properly. In this context, the use of dedicated hardware for real-time aquaponic monitoring can greatly resolve the issue of inexperienced handlers. In this article, we present a complete methodology to train a deep neural network to perform fish size estimation in real time. To achieve high accuracy, a novel implementation of swish function is presented. This novel version is far more hardware efficient than the original one, while being extremely accurate. Moreover, we present a deep learning accelerator that can classify 40 million fish samples in a second. The dedicated real-time system is about 1600 times faster than the one based on general-purpose computers. The proposed neuromorphic accelerator consumes about 2600 slice registers on a low-end model of Virtex 6 FPGA series.

Low computational demand stray light correction method for hyperspectral imaging spectrometers

Stray light correction in hyperspectral imaging spectrometers has long been restricted by high computational requirements. This paper presents a low computational demand method, based on the matrix operations for spectrometer stray light correction, using an iterative approach to efficiently correct stray light across both spectral and spatial dimensions. The efficacy of this method is demonstrated through its application to simulated and real images, achieving an overall reduction of stray light by over 50%, with significantly reduced computation time and memory usage compared to the method by Zong et al. based on a sparse matrix [Appl. Opt. 45, 1111 (2006)10.1364/AO.45.001111APOPAI2155-3165]. By enabling stray light correction on general-purpose computers, this method enhances affordability and accessibility, promoting broader use and reducing measurement uncertainties in various hyperspectral imaging applications.

Computation Foretold: Ada Lovelace's wisdom about the first general-purpose computer is buried in the appendix of a paper.

Computation Foretold: Ada Lovelace's wisdom about the first general-purpose computer is buried in the appendix of a paper.

Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems—Overview, Challenges, and Opportunities

Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems—Overview, Challenges, and Opportunities

Parallel implementation for real-time visual SLAM systems based on heterogeneous computing

Simultaneous localization and mapping has become rapidly developed and plays an indispensable role in intelligent vehicles. However, many state-of-the-art visual simultaneous localization and mapping (VSLAM) frameworks are very time-consuming both in front-end and back-end, especially for large-scale scenes. Nowadays, the increasingly popular use of graphics processors for general-purpose computing, and the progressively mature high-performance programming theory based on compute unified device architecture (CUDA) have given the possibility for large-scale VSLAM to solve the conflict between limited computing power and excessive computing tasks. The paper proposes a full-flow optimal parallelization scheme based on heterogeneous computing to speed up the time-consuming modules in VSLAM. Firstly, a parallel strategy for feature extraction and matching is designed to reduce the time consumption arising from multiple data transfers between devices. Secondly, a bundle adjustment method based solely on CUDA is developed. By fully optimizing memory scheduling and task allocation, a large increase in speed is achieved while maintaining accuracy. Besides, CUDA heterogeneous acceleration is fully utilized for tasks such as error computation and linear system construction in the VSLAM back-end to enhance the operation speed. Our proposed method is tested on numerous public datasets on both computer and embedded sides, respectively. A number of qualitative and quantitative experiments are performed to verify its superiority in terms of speed compared to other states-of-the-art.

Deep Learning-Based Synthetic Skin Lesion Image Classification.

Advances in general-purpose computers have enabled the generation of high-quality synthetic medical images that human eyes cannot differ between real and AI-generated images. To analyse the efficacy of the generated medical images, this study proposed a modified VGG16-based algorithm to recognise AI-generated medical images. Initially, 10,000 synthetic medical skin lesion images were generated using a Generative Adversarial Network (GAN), providing a set of images for comparison to real images. Then, an enhanced VGG16-based algorithm has been developed to classify real images vs AI-generated images. Following hyperparameters tuning and training, the optimal approach can classify the images with 99.82% accuracy. Multiple other evaluations have been used to evaluate the efficacy of the proposed network. The complete dataset used in this study is available online to the research community for future research.

Communication-Efficient Multi-Party Computation for RMS Programs

Despite much progress, general-purpose secure multi-party computation (MPC) with active security may still be prohibitively expensive in settings with large input datasets. This particularly applies to the secure evaluation of graph algorithms, where each party holds a subset of a large graph. Recently, Araki et al. (ACM CCS '21) showed that dedicated solutions may provide significantly better efficiency if the input graph is sparse. In particular, they provide an efficient protocol for the secure evaluation of “message passing” algorithms, such as the PageRank algorithm. Their protocol's computation and communication complexity are both O ~ ( M · B ) instead of the O ( M 2 ) complexity achieved by general-purpose MPC protocols, where M denotes the number of nodes and B the (average) number of incoming edges per node. On the downside, their approach achieves only a relatively weak security notion; 1 -out-of- 3 malicious security with selective abort. In this work, we show that PageRank can instead be captured efficiently as a restricted multiplication straight-line (RMS) program, and present a new actively secure MPC protocol tailored to handle RMS programs. In particular, we show that the local knowledge of the participants can be leveraged towards the first maliciously-secure protocol with communication complexity linear in M , independently of the sparsity of the graph. We present two variants of our protocol. In our communication-optimized protocol, going from semi-honest to malicious security only introduces a small communication overhead, but results in quadratic computation complexity O ( M 2 ) . In our balanced protocol, we still achieve a linear communication complexity O ( M ) , although with worse constants, but a significantly better computational complexity scaling with O ( M · B ) . Additionally, our protocols achieve security with identifiable abort and can tolerate up to n − 1 corruptions.

Implementation and testing of parallel PSO to attain speedup on general purpose computer systems

Implementation and testing of parallel PSO to attain speedup on general purpose computer systems

Accelerating electrostatic particle-in-cell simulation: A novel FPGA-based approach for efficient plasma investigations.

Particle-in-cell (PIC) simulation serves as a widely employed method for investigating plasma, a prevalent state of matter in the universe. This simulation approach is instrumental in exploring characteristics such as particle acceleration by turbulence and fluid, as well as delving into the properties of plasma at both the kinetic scale and macroscopic processes. However, the simulation itself imposes a significant computational burden. This research proposes a novel implementation approach to address the computationally intensive phase of the electrostatic PIC simulation, specifically the Particle-to-Interpolation phase. This is achieved by utilizing a high-speed Field Programmable Gate Array (FPGA) computation platform. The suggested approach incorporates various optimization techniques and diminishes memory access latency by leveraging the flexibility and performance attributes of the Intel FPGA device. The results obtained from our study highlight the effectiveness of the proposed design, showcasing the capability to execute hundreds of functional operations in each clock cycle. This stands in contrast to the limited operations performed in a general-purpose single-core computation platform (CPU). The suggested hardware approach is also scalable and can be deployed on more advanced FPGAs with higher capabilities, resulting in a significant improvement in performance.

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT) domain require complex on-device signal analysis and data reduction to maximize energy efficiency on these energy-constrained devices. Coarse-grained reconfigurable architectures (CGRAs) have been proposed as a good compromise between flexibility and energy efficiency for ultra-low power (ULP) signal processing. Existing CGRAs are often specialized and domain-specific or can only accelerate simple kernels, which makes accelerating complete applications on a CGRA while maintaining high energy efficiency an open issue. Moreover, the lack of instruction set architecture (ISA) standardization across CGRAs makes code generation using current compiler technology a major challenge. This work introduces R-Blocks; a ULP CGRA with HW/SW co-design tool-flow based on the OpenASIP toolset. This CGRA is extremely flexible due to its well-established VLIW-SIMD execution model and support for flexible SIMD-processing, while maintaining an extremely high energy efficiency using software bypassing, optimized instruction delivery, and local scratchpad memories. R-Blocks is synthesized in a commercial 22-nm FD-SOI technology and achieves a full-system energy efficiency of 115 MOPS/mW on a common FFT benchmark, 1.45× higher than a highly tuned embedded RISC-V processor. Comparable energy efficiency is obtained on multiple complex workloads, making R-Blocks a promising acceleration target for general-purpose computing.

The Role of the Supercomputer in the Modern World of Innovative Technologies

What is a supercomputer and why is it needed? What place does it occupy among computing equipment? Thanks to this article, we will determine the evolution and role of the supercomputer in the modern world and in the life of an average citizen. A supercomputer is a class of the most powerful computer systems available, which are evaluated in comparison with currently existing general purpose computer systems and the level of technology development. In general, the term "supercomputer" refers to a complex of server computers. All of them are connected to each other and work in parallel through a high-speed network. The similarity of a home computer and a supercomputer lies in their functions – data storage and processing, belonging to the same von Neumann architecture (the architecture of computing machines, the feature of which is the joint storage of data and machine commands in cells of the same memory). But the difference is huge in quantitative characteristics: these are the arrays of data that can be processed on these devices and the speed of performing the assigned tasks. By the way, a new unit of measurement – FLOPS – was proposed for measuring the speed of supercomputers. It is thanks to this value that performance is measured - the higher the number, the more powerful the computer is and which serves as the basis for ranking supercomputers. Today, supercomputers help solve a number of tasks in various fields – medicine, physics, mathematics, energy, etc. and are considered advanced computing technology. Traditionally, supercomputers are not considered rare: their development is ongoing and they bring a lot of benefits in many areas. In the future, powerful computing machines can become the main assistants in fields closely related to machine learning and artificial intelligence. Keywords: supercomputer, development evolution, computer architecture, FLOPS.

Heralded Three-Photon Entanglement from a Single-Photon Source on a Photonic Chip.

In the quest to build general-purpose photonic quantum computers, fusion-based quantum computation has risen to prominence as a promising strategy. This model allows a ballistic construction of large cluster states which are universal for quantum computation, in a scalable and loss-tolerant way without feed forward, by fusing many small n-photon entangled resource states. However, a key obstacle to this architecture lies in efficiently generating the required essential resource states on photonic chips. One such critical seed state that has not yet been achieved is the heralded three-photon Greenberger-Horne-Zeilinger (3-GHZ) state. Here, we address this elementary resource gap, by reporting the first experimental realization of a heralded 3-GHZ state. Our implementation employs a low-loss and fully programmable photonic chip that manipulates six indistinguishable single photons of wavelengths in the telecommunication regime. Conditional on the heralding detection, we obtain the desired 3-GHZ state with a fidelity 0.573±0.024. Our Letter marks an important step for the future fault-tolerant photonic quantum computing, leading to the acceleration of building a large-scale optical quantum computer.

Accelerating range minimum queries with ray tracing cores

Over the past decade, GPU technology has undergone a notable transformation, evolving from pure general-purpose computation to the integration of application-specific integrated circuits (ASICs), including Tensor Cores and Ray Tracing (RT) cores. While these specialized GPU cores were initially developed to enhance specific domains like AI and real-time rendering, recent research has successfully harnessed their capabilities to expedite other tasks traditionally reliant on conventional GPU computing. One GPU task that is still yet to find its way into RT cores is the processing of range minimum queries (RMQs) in parallel, which is fundamental in fields such as information retrieval or pattern matching, among others. In this context, accelerating RMQs with RT cores would impact many of the applications that heavily rely on this task. In this work we present RTXRMQ, a new approach that can compute RMQs with RT cores. The main contribution is the proposal of a geometric solution for RMQ, where elements become triangles that are placed and shaped according to the element’s value and position in the array, respectively, such that the closest hit of a ray launched from a point given by the query parameters corresponds to the result of that query. Experimental results show that RTXRMQ is currently best suited for small query ranges relative to the input size, achieving up to 5× and 2.3× of speedup over parallel state of the art CPU and GPU approaches, respectively. For medium and large query ranges RTXRMQ is still slower than the state of the art GPU approach, but still competitive by being 2.5× and 4× faster than a state of the art CPU method running in parallel as well. Furthermore, performance scaling experiments across the latest RTX GPU architectures show that if the current RT core scaling trend continues, then RTXRMQ’s performance would scale at a higher rate than the other compared approaches, making it an attractive tool for future high performance applications that employ many batches of RMQs.

Comparative study of CUDA-based parallel programming in C and Python for GPU acceleration of the 4th order Runge-Kutta method

In this paper, a comparative study is presented on the application of General-purpose Computing on Graphics Processing Units for solving the point reactor kinetics equations through the utilization of the 4th Order Runge-Kutta (RK4) method using the programming languages C and Python. Sequential and parallel algorithms of the RK4 method were developed in C/C++ and Python, with parallel algorithms specifically designed to operate on Graphics Processing Units (GPUs) utilizing the NVIDIA Compute Unified Device Architecture (CUDA) as the programming platform. As an experiment, the execution time for the sequential and parallel algorithms were compared for a reactivity value of ρ = 0.003 and a simulation time of t = 100 s. The parallel C and Python algorithms achieved, respectively, speedups of 9.33 and 409.7 when comparing the execution time on the best GPU utilized (RTX 3070Ti) with the best CPU (3600XT), while still maintaining numerical precision.

Optimizing convolutional neural networks for IoT devices: performance and energy efficiency of quantization techniques

This document addresses some inherent problems in Machine Learning (ML), such as the high computational and energy costs associated with their implementation on IoT devices. It aims to study and analyze the performance and efficiency of quantization as an optimization method, as well as the possibility of training ML models directly on an IoT device. Quantization involves reducing the precision of model weights and activations while still maintaining acceptable levels of accuracy. Using representative networks for facial recognition developed with TensorFlow and TensorRT, Post-Training Quantization and Quantization-Aware Training are employed to reduce computational load and improve energy efficiency. The computational experience was conducted on a general-purpose computer featuring an Intel i7-1260P processor and an NVIDIA RTX 3080 graphics card used as an accelerator. Additionally, a NVIDIA Jetson AGX Orin was used as an example of an IoT device. We analyze the feasibility of training on an IoT device, the impact of quantization optimization on knowledge transfer-trained models and evaluate the differences between Post-Training Quantization and Quantization-Aware Training in such networks on different devices. Furthermore, the performance and efficiency of NVIDIA’s inference accelerator (Deep Learning Accelerator - DLA, in its 2.0 version) available at the Jetson Orin architecture are studied. We concluded that the Jetson device is capable of performing training on its own. The IoT device can achieve inference performance similar to that of the more powerful processor, thanks to the optimization process, with better energy efficiency. Post-Training Quantization has shown better performance, while Quantization-Aware Training has demonstrated higher energy efficiency. However, since the accelerator cannot execute certain layers of the models, the use of DLA worsens both the performance and efficiency results.

High Speed and Area Efficient Scalable n-Bit Digital Comparator

Abstract: The digital comparator is a crucial design element in various applications, including scientific computations. It is optimized for general-purpose computer architecture, memory addressing logic, queue buffers, and test circuits. High-speed comparators are essential for arithmetic operations, data sorting, and decision-making processes in digital systems. Area efficiency is crucial in integrated circuit design, as it minimizes the physical space a comparator occupies on a chip, reducing manufacturing costs and optimizing performance. The term "scalable" means the comparator can be adapted to handle different word lengths (n-bit), making it versatile for various applications. This project proposes an area-efficient n-bit digital comparator with high operating speed and low-power dissipation. The comparator structure consists of two modules: the Comparison Evaluation Module (CEM) and the Final Module (FM). The CEM involves the regular structure of repeated logic cells used for parallel prefix tree structure, while the FM validates the final comparison based on results from the CEM. The design is implemented using Tanner EDA in 45nm technology

An open-source application software for spatial prediction of permanent displacements in earthquake-induced landslides by the Newmark sliding block method: pyNewmarkDisp

This paper presents pyNewmarkDisp, an open-source application software developed in Python for calculating the spatial distribution of permanent displacements (up) in earthquake-triggered shallow landslides through the Newmark sliding block method. up are often estimated by simplified methods using empirical correlations instead of the direct Newmark method in which ground motion accelerations exceeding a critical value are integrated twice. These simplified procedures have traditionally been justified because of the time consumption, labor intensiveness, and impracticality of the direct Newmark method at large spatial scales. However, pyNewmarkDisp has a well-optimized code taking advantage of NumPy array operations and just-in-time Numba compilation that allows performing the direct Newmark method at large-scale spatial domains, even on general-purpose computers. pyNewmarkDisp is exemplified through a hypothetical study case, and its results are compared to three empirical correlations, showing significant differences and confirming that simplified methods can lead to inaccurate results.