General-purpose Central Processing Unit Research Articles

A Survey of Network-Based Hardware Accelerators

Many practical data-processing algorithms fail to execute efficiently on general-purpose CPUs (Central Processing Units) due to the sequential matter of their operations and memory bandwidth limitations. To achieve desired performance levels, reconfigurable (FPGA (Field-Programmable Gate Array)-based) hardware accelerators are frequently explored that permit the processing units’ architectures to be better adapted to the specific problem/algorithm requirements. In particular, network-based data-processing algorithms are very well suited to implementation in reconfigurable hardware because several data-independent operations can easily and naturally be executed in parallel over as many processing blocks as actually required and technically possible. GPUs (Graphics Processing Units) have also demonstrated good results in this area but they tend to use significantly more power than FPGA, which could be a limiting factor in embedded applications. Moreover, GPUs employ a Single Instruction, Multiple Threads (SIMT) execution model and are therefore optimized to SIMD (Single Instruction, Multiple Data) operations, while in FPGAs fully custom datapaths can be built, eliminating much of the control overhead. This review paper aims to analyze, compare, and discuss different approaches to implementing network-based hardware accelerators in FPGA and programmable SoC (Systems-on-Chip). The performed analysis and the derived recommendations would be useful to hardware designers of future network-based hardware accelerators.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

Redesigned TDM-PON System Architecture Based on Point-to-Point Ethernet Transmission and Software Processing With General-Purpose Hardware

This article proposes a novel architecture of a time division multiplexing passive optical network (TDM-PON) system with general-purpose hardware. The system operates with the point-to-point (P2P) Ethernet protocol and software processing. The architecture is redesigned from the ground up, differing from conventional PON system architectures. In recent years, researchers have attempted to softwarize a number of PON functions such as media access control (MAC) and physical functions, which run on a general-purpose central processing unit (CPU). On the other hand, these existing systems still required PON-dedicated or programmable hardware for processing the PON specific protocol. This paper proposes a TDM-PON system that requires only general-purpose hardware; a network interface card with the use of the P2P Ethernet protocol and a general-purpose server with the use of software processing. To operate the proposed system, we newly developed burst-mode operation and multipoint MAC control schemes, while taking Link Fault Signaling and CPU processing jitter into account. We quantitatively evaluated the burst-mode transmission with P2P generic Ethernet TRx as a preliminary experiment, which showed that T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> were 75 μs and less than 1 μs, respectively. Then, we measured our developed prototype system's performance for verifying the feasibility of our proposal. In specific, it achieved a 5.2 Gbps PON system consisting of an optical line terminal (OLT) server and two optical network unit (ONU) servers under the condition of a 500-ms grant cycle including a 100-ms discovery window.

SIMT-X

This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units (GPUs)-style SIMT execution across multiple threads of the same program for high throughput, while retaining the latency benefits of out-of-order execution, and the programming convenience of homogeneous multi-thread processors. SIMT-X leverages the existing Single Instruction Multiple Data (SIMD) back-end to provide CPU/GPU-like processing on a single core with minimal overhead. We demonstrate that although SIMT-X invokes a restricted form of Out-of-Order (OoO), the microarchitecture successfully captures a majority of the benefits of aggressive OoO execution using at most two concurrent register mappings per architectural register, while addressing issues of partial dependencies and supporting a general-purpose Instruction Set Architecture (ISA).

Energy Optimization by Software Prefetching for Task Granularity in GPU-Based Embedded Systems

Energy saving and optimization play an increasingly important role in industrial electronic systems. A heterogeneous embedded system is composed of a general-purpose central processing unit with an enhanced module of graphics processing units (GPU). This article explores the effective strategies of task granularity and software prefetching for energy optimization. In this article, we propose a novel energy optimization model for GPU-based embedded systems by harnessing a communication-based pipeline spatial and temporal relation. We analyze the characteristics of a multiple thread execution of parallel GPUs. We present an effective algorithm for the dynamic power optimization with the adaptively adjusted distance of software prefetching. The experimental results show that the dynamic energy consumption can be saved by 22.1% and 21.8%, respectively, under two prefetching strategies (register and shared memory) without loss of performance. We demonstrate the effectiveness of the proposed methods for energy saving and consumption reduction of performance driven computing in industrial scenarios.

Efficient Object Detection Framework and Hardware Architecture for Remote Sensing Images

Object detection in remote sensing images on a satellite or aircraft has important economic and military significance and is full of challenges. This task requires not only accurate and efficient algorithms, but also highperformance and low power hardware architecture. However, existing deep learning based object detection algorithms require further optimization in small objects detection, reduced computational complexity and parameter size. Meanwhile, the generalpurpose processor cannot achieve better power efficiency, and the previous design of deep learning processor has still potential for mining parallelism. To address these issues, we propose an efficient contextbased feature fusion single shot multibox detector (CBFFSSD) framework, using lightweight MobileNet as the backbone network to reduce parameters and computational complexity, adding feature fusion units and detecting feature maps to enhance the recognition of small objects and improve detection accuracy. Based on the analysis and optimization of the calculation of each layer in the algorithm, we propose efficient hardware architecture of deep learning processor with multiple neural processing units (NPUs) composed of 2D processing elements (PEs), which can simultaneously calculate multiple output feature maps. The parallel architecture, hierarchical onchip storage organization, and the local register are used to achieve parallel processing, sharing and reuse of data, and make the calculation of processor more efficient. Extensive experiments and comprehensive evaluations on the public NWPU VHR10 dataset and comparisons with some stateoftheart approaches demonstrate the effectiveness and superiority of the proposed framework. Moreover, for evaluating the performance of proposed hardware architecture, we implement it on Xilinx XC7Z100 field programmable gate array (FPGA) and test on the proposed CBFFSSD and VGG16 models. Experimental results show that our processor are more power efficient than general purpose central processing units (CPUs) and graphics processing units (GPUs), and have better performance density than other stateoftheart FPGAbased designs.

The Computational Efficiency of Monte Carlo Breakage of Articles using Serial and Parallel Processing: A Comparison

This paper presents a GPU-based parallelized and a CPU-based serial Monte-Carlo method for breakage of a particle. We compare the efficiency of the graphic card’s graphics processing unit (GPU) and the general-purpose central processing unit (CPU), in a simulation using Monte Carlo (MC) methods for processing the particle breakage. Three applications are used to compare the computational performance times, clock cycles and speedup factors, to find which platform is faster under which conditions. The architecture of the GPU is becoming increasingly programmable; it represents a potential speedup for many applications compared to the modern CPU. The objective of the paper is to compare the performance of the GPU and Intel Core i7-4790 multicore CPU. The implementation for the CPU was written in the C programming language, and the GPU implemented the kernel using Nvidia’s CUDA (Compute Unified Device Architecture). This paper compares the computational times, clock cycles and the speedup factor for a GPU and a CPU, with various simulation settings such as the number of simulation entries (SEs), for a better understanding of the GPU and CPU computational efficiency. It has been found that the number of SEs directly affects the speedup factor.

Efficient GPU and CPU-based LDPC decoders for long codewords

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard—at the high data rates required for television broadcasting—possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.

SU‐GG‐I‐173: GPU‐Accelerated Digitally Reconstructed Radiograph Generation for Radiation Therapy

Purpose: To evaluate the speed up and image quality for digitally reconstructed radiograph (DRR) calculations using a graphic processing unit (GPU) comparing with a central processing unit (CPU). Method and Materials: We developed an application for DRR image calculations using a faster incremental Siddon ray tracing algorithm. The implementation of the core integration loop was the same for the CPU and the GPU except that single‐precision operations were used on the GPU with CUDA 1.2. The GPU runs on NVIDIA GeForce GTX 280M with 1 GB video memory. To validate the correctness of the algorithm, we employed a clinical three‐field plan as an example. The CT volume image and the RT plan were exported from a commercial treatment planning system and read by our application to generate the DRR images. Results: By comparing visually with the bony structures from our DRR images and the commercial software generated DRR images, we have confidence in the correctness of our fast ray tracing implementation on both CPU and GPU. The accuracy of the GPU calculations comparing with the CPU calculation is well acceptable as only about 3% of the total pixels have less than 0.1% pixel values difference from the CPU calculations for the test fields. Conclusions: The DRR calculations using GPU is more than an order of magnitude faster than using a general purpose CPU. The image quality by the two methods is very similar where the difference comes from the float point operation type. This accelerated DRR computation has potential to reduce the patient‐positioning time during the 2D/3D registration where inline DRR calculations are required in the iteration.

Multicore Image Processing with OpenMP [Applications Corner

One of the recent innovations in computer engineering has been the development of multicore processors, which are composed of two or more independent cores in a single physical package. Today, many processors, including digital signal processors (DSPs), mobile, graphics, and general-purpose central processing units (CPUs) have a multicore design, driven by the demand of higher performance. Major CPU vendors have changed strategy away from increasing the raw clock rate to adding on-chip support for multithreading by increases in the number of cores; dual and quad-core processors are now commonplace. Signal and image processing programmers can benefit dramatically from these advances in hardware, by modifying single-threaded code to exploit parallelism to run on multiple cores.

Fast Maximum Intensity Projections of Large Medical Data Sets by Exploiting Hierarchical Memory Architectures

Maximum intensity projections (MIPs) are an important visualization technique for angiographic data sets. Efficient data inspection requires frame rates of at least five frames per second at preserved image quality. Despite the advances in computer technology, this task remains a challenge. On the one hand, the sizes of computed tomography and magnetic resonance images are increasing rapidly. On the other hand, rendering algorithms do not automatically benefit from the advances in processor technology, especially for large data sets. This is due to the faster evolving processing power and the slower evolving memory access speed, which is bridged by hierarchical cache memory architectures. In this paper, we investigate memory access optimization methods and use them for generating MIPs on general-purpose central processing units (CPUs) and graphics processing units (GPUs), respectively. These methods can work on any level of the memory hierarchy, and we show that properly combined methods can optimize memory access on multiple levels of the hierarchy at the same time. We present performance measurements to compare different algorithm variants and illustrate the influence of the respective techniques. On current hardware, the efficient handling of the memory hierarchy for CPUs improves the rendering performance by a factor of 3 to 4. On GPUs, we observed that the effect is even larger, especially for large data sets. The methods can easily be adjusted to different hardware specifics, although their impact can vary considerably. They can also be used for other rendering techniques than MIPs, and their use for more general image processing task could be investigated in the future.

Radio link enhancement using an open flexible protocol stack framework

AbstractThis paper explores radio link enhancement utilising dynamic run‐time software download and configuration. In particular, the insertion of virtual medium access control (MAC), hybrid automatic repeat request (ARQ) and compression enhancement layers are considered in this paper. This is made possible with a flexible protocol stack framework, which permits the insertion of protocol layers and configuring them in a platform‐independent manner. A general purpose central processing unit (CPU) environment is used in order to assess performance and power consumption of this proposed approach. The results presented indicate that there are scenarios in which this approach is attractive and that execution environment optimisations for performing generic protocol functions can increase the applicability to more scenarios.Currently protocols, and in particular link layer protocols, are designed to support specific traffic and underlying radio propagation characteristics and network topologies that are expected to be observed in a range of deployment scenarios in a manner that is determined at a system design time. As a result, this leads to many different solutions that are tailored to the particular and quite specific requirements such as short range personal area networks (PAN) based on bluetooth or ultra wide band (UWB), local area networks (LAN) based on 802.11 and of course many wide area cellular networks. These solutions cannot be changed to support traffic characteristics and radio performance observed in scenarios that were not envisaged at the time of standardisation. Hence, many new releases of standards are generated to incorporate these new and often optional features that often cannot be used because not all devices support these features. A flexible protocol stack framework has been proposed to provide the ability to insert and configure new software protocol implementations at run time. The overall benefit of this is that new optional features can be exploited before or without standardisation. In addition, dynamic optimisation can be performed to tailor the protocol configuration to specific scenarios and adapt to the changing radio environment. Copyright © 2005 John Wiley &amp; Sons, Ltd.

What is a microprocessor?

A microprocessor is the decision-making/data-manipulating portion of a microcomputer system just as is the central processing unit (CPU) of a minior macrocomputer system (macro is a convenient term used to refer to large-scale mainframes). The distinction is somewhat blurred with respect to the classifications between minicomputers and large-scale computers. This is even more so between minicomputers and microcomputers. The main distinctions have to do with size, speed, and cost factors. In point of fact, a microprocessor may be defined as a oneor few-chip integrated circuit (IC) realization of a general purpose CPU. (The term IC refers to the electronic fabrication technology involved in manufacturing the microprocessor. This term will be explained in more detail later.) The microprocessor contains registers (temporary, or working storage), control circuitry, and data paths for interpretation and execution of instructions? The primary difference between the larger CPUs and the microprocessor is size. This stems from the fact that the larger CPUs are made up of many individual physical components and the microprocessor is a single physical device. Figure 1 shows this relationship between the CPU of a NOVA 820 minicomputer and an INTEL 8080 microprocessor. The microprocessor is a single programmable logic device, which may act as the heart of a computer system (i.e., be a CPU) or may find use in a myriad of other devices (i.e., be a controller). In particular, microprocessors today are found in automobile ignition systems, washing machines, microwave ovens, and intelligent laboratory instruments. The extreme versatility, low cost, and high reliability of these devices have brought about a revolution in the electronics industry as well as in every other field that utilizes devices to control or monitor situations through electronic means.