Ge Stack Research Articles

Investigation on the passivation, band alignment, gate charge, and mobility degradation of the Ge MOSFET with a GeO x /Al2O3 gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

Investigation on Ge0.8Si0.2-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice.

For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO3 temperatures between Ge and p+-Ge0.8Si0.2 were obtained. In p+-Ge0.8Si0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO3 temperature of 20 °C. The etch rate and the selectivity were affected by HNO3 temperatures. As the HNO3 temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary Id–Vds output characteristic curves of Ge vGAAFET were provided.

Atomic and electronic structures of Si/Ge(100) interfaces studied by high-resolution photoelectron spectroscopy and scanning tunneling microscopy

The close similarity of silicon and germanium, isoelectronic group-IV elements, makes the integration of Ge layers on Si substrates suitable for technology development, but the atomic and electronic structures of ${\mathrm{Si}}_{1\ensuremath{-}x}{\mathrm{Ge}}_{x}$ surfaces are still an open issue, in particular, for the alloy systems where Si is deposited on the Ge substrate. In this study, utilizing low-energy electron diffraction, scanning tunneling microscopy, and photoelectron spectroscopy using synchrotron radiation, we demonstrate that the formation mechanisms of the Si-on-Ge structures are controlled by two interface phenomena, namely Si indiffusion and Ge segregation on top of this surface. Employing these phenomena and controlling the Si quantity, one can synthesize the well-defined crystalline Ge-(2 \ifmmode\times\else\texttimes\fi{} 1)/${\mathrm{Si}}_{1\ensuremath{-}x}{\mathrm{Ge}}_{x}$/Ge(100) stacks where the number of Si atoms at the host Ge lattice sites can be tuned. Using the obtained data on the atomic and electronic structures of such systems, we also propose a method for interface engineering of Ge/Si/Ge stacks with tailored properties as promising templates for growing the device junctions.

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/high-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium.

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Frequency and Area Dependence of High-K/Ge Mos Capacitors

– Ge substrate devices in Complementary Metal Oxide Semiconductors (CMOS) technology have been extensively studied due to its high electron and hole mobility [1]. However, most of the Ge devices have some limitation as making a high-quality Ge/High-k gate stack is rather difficult compared to Si/High-k system. The purpose of this work is to further study the capacitance measurements of a MOS capacitor at different frequencies for square devices with different side lengths (10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm). The series resistance corrected capacitance (Cc) for accumulation region increases on a faster pace when a lower frequency (1KHz) is used than at a higher frequency (1MHz) (Figure 1(a)) as a function of side length, a. Accumulation capacitance has a strong dependence on frequency in metal oxide semiconductor devices. Our devices follow the same trend as previous studies have reported [2]. On the other hand, our study shows substantial decrease of Cc per unit area in Ge/High-K in comparison to High-K/Si devices (Figure 1(b)). This decrease is attributed to the large non-uniform interface defect density [3], high leakage current [3] associated with Ge stacks and fringing field effect [4]. Capacitance at accumulation condition depends on interface capacitance (Cit) which changes with defects density. Defect density increases proportionally with area and High-K/Ge devices, being leakier, experience a higher decrease of Cc per unit area than High-K/Si devices. The impact of fringing field capacitance (CL) on parallel plate capacitance (CP) decreases when device area is increased (Figure 1(c)) and this contributes to further decrease in total capacitance Cc per unit area. This work explains the frequency dispersion of high-k MOS capacitance in accumulation region and the unit capacitance decrease when Ge substrate is used. The study also models the fringing field capacitance [5] and its effect on MOS devices. Figure 1 (a) Corrected capacitance (C c) measured at -1.5 V (accumulation) at 1 MHz and 1 KHz shows frequency dependence; (b) Unit Capacitance is plotted against area for Ge substrate and Si substrate sample for measurements at frequency of 1MHz. C s is substrate capacitance and C ox is oxide capacitance; (c) CL/CP as a function of area. CL and CP are calculated as per Yuan & Trick’s model [5]. [1] D. Kuzum, A. J. Pethe, T. K., K. C. S, IEEE T. Electron. Dev., vol. 56, p. 648, 2009. [2] P. R. Lee, J. R. Ruzyllo, Electrochemical Society, vol. 9, p.353-362, 2007. [3] Y. M. Ding, D. Misra, J. Vac. Sci. Technol. B, vol. 34, p. 021203 2016. [4] S. Maurya, B. R. Singh, Solid States Physics, AIP Conf. Proc. 1512, 742-743, 2013. [5] E. Barke, IEEE Transactions on Computer Aided Design, vol. 7, No. 2, 1988. Figure 1

Effect of Remote Oxygen Scavenging on Electrical Properties of Ge-Based Metal–Oxide–Semiconductor Capacitors

Remote oxygen scavenging has been studied in a metal/high-k dielectric/GeO2/Ge stack, where a thin Ti layer inserted into the metal/high-k dielectric interface serves as the scavenger. First, we established that remote oxygen scavenging indeed occurs specifically in the studied HfO2/Al2O3/GeO2/Ge stack. It was also established that the source for oxygen is decomposition of the GeO2 layer. Then, the effect of remote oxygen scavenging of the GeO2 layer on the electrical characteristics of the metal/oxide/Ge capacitors was investigated. The electrical properties were studied in comparison with identical gate stacks with a Pt electrode, before and after annealing. Although a decrease in effective oxide thickness was demonstrated as a result of this process, clear degradation of the interface electrical quality was observed after scavenging. Initiation of the scavenging process was witnessed upon deposition of Ti at room temperature, emphasizing that this process could not be controlled.

Evolution of interface chemistry and dielectric properties of HfO2/Ge gate stack modulated by Gd incorporation and thermal annealing

In current work, effects of rapid thermal annealing (RTA) on the interface chemistry and electrical properties of Gd-doped HfO2 (HGO)/Ge stack have been investigated systematically. It has been demonstrated that the presence of GeOx interfacial layer between HfGdO and Ge is unavoidable and appropriate annealing can improve metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, frequency dispersion, and leakage current. The involved leakage current conduction mechanisms for metal-oxide-semiconductor (MOS) capacitors based on sputtered HGO/Ge gate stacks with optimal annealed temperature also have been discussed in detail. As a result, the Al/HGO barrier height and the band offset of HGO/Ge gate stack have been determined precisely.

Oxygen Transport and Incorporation in Pt/HfO2 Stacks Deposited on Germanium and Silicon

Ge is a promising material to improve transistor performance. However, finding an efficient passivation strategy for this semiconductor is still a challenge. Annealing in O2 of metal/dielectric stacks prepared on Ge can improve the electrical properties of the final structure. However, excessive Ge oxidation cannot take place. O isotopic tracing in conjunction with subnanometric depth profiling of 18O were used to investigate oxygen transport and incorporation in Pt/HfO2/(Ge or Si) stacks. The supply of atomic oxygen (able to diffuse through HfO2) is a function of temperature and the number of available O2 dissociation sites in HfO2. A Pt top layer promotes a more efficient O2 dissociation, resulting in a higher O exchange in HfO2 and a higher O supply at the HfO2/semiconductor interface. The different nature of the native oxides of Si and Ge has a direct influence on the resulting physicochemical modifications of the stacks prepared on these semiconductor materials.

Structural and thermodynamic consideration of metal oxide doped GeO2 for gate stack formation on germanium

A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO2) on Ge. We propose two criteria on the selection of desirable M-GeO2 for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO2 network, benefiting the thermal stability and water resistance in M-GeO2/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO2/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

Direct observation of both contact and remote oxygen scavenging of GeO2 in a metal-oxide-semiconductor stack

In the path to incorporating Ge based metal-oxide-semiconductor into modern nano-electronics, one of the main issues is the oxide-semiconductor interface quality. Here, the reactivity of Ti on Ge stacks and the scavenging effect of Ti were studied using synchrotron X-ray photoelectron spectroscopy measurements, with an in-situ metal deposition and high resolution transmission electron microscopy imaging. Oxygen removal from the Ge surface was observed both in direct contact as well as remotely through an Al2O3 layer. The scavenging effect was studied in situ at room temperature and after annealing. We find that the reactivity of Ti can be utilized for improved scaling of Ge based devices.

Enhancement of thermal stability and water resistance in yttrium-doped GeO2/Ge gate stack

We have systematically investigated the material and electrical properties of yttrium-doped GeO2 (Y-GeO2) on Germanium (Ge). A significant improvement of both thermal stability and water resistance were demonstrated by Y-GeO2/Ge stack, compared to that of pure GeO2/Ge stack. The excellent electrical properties of Y-GeO2/Ge stacks with low Dit were presented as well as enhancement of dielectric constant in Y-GeO2 layer, which is beneficial for further equivalent oxide thickness scaling of Ge gate stack. The improvement of thermal stability and water resistance are discussed both in terms of the Gibbs free energy lowering and network modification of Y-GeO2.

Ge diffusion and bonding state change in metal/high-k/Ge gate stacks and its impact on electrical properties

Graphical abstractDisplay Omitted Plasma-assisted oxidation is preferable to form HfO2/GeOx/Ge structures.Al on HfO2/GeOx/Ge stack induces the reduction of GeOx and Al germanide formation.Hf germanide was formed in Pt/HfO2/GeOx/Ge stacks by annealing.Germanide formation should be suppressed for high-quality metal/high-k/Ge stack. We systematically investigated Ge diffusion and chemical bonding states in metal/high-k/Ge gate stacks by synchrotron radiation photoemission spectroscopy (SR-PES) to understand their impact on electrical properties. Although Hf germanide was found in both Ge 3s and Hf 4f spectra for HfO2/GeOx/Ge gate stacks formed by ultrathin metal Hf deposition and subsequent in situ low-pressure thermal oxidation, such germanide could be fully oxidized when using plasma-assisted oxidation. However, Al electrode deposition on HfO2/GeOx/Ge stacks was found to reduce interfacial GeOx layer, resulting in the formation of Al germanide at the Al/HfO2 interface even at room temperature. No germanide was formed in the stacks with inert Pt electrode. This indicates that the Al layer may promote upward diffusion of GeO molecules through the HfO2 layer. The thermal stability of metal/HfO2/GeOx/Ge gate stacks was also evaluated by in situ SR-PES. Hf germanide was observed to form near the HfO2/GeOx interface probably due to Ge atoms intermixing in the HfO2 layer in the Pt-gate stacks, in contrast to the enhanced formation of Al germanide in Al-gate stacks. Electrical characterization revealed that the formation of metal germanide led to severe degradation of insulating properties in metal/high-k/Ge stacks.

Water Growth on GeO2/Ge(100) Stack and Its Effect on the Electronic Properties of GeO2

Water growth on GeO2 films on a Ge(100) substrate and their effect on the electronic properties of GeO2 films are investigated using ambient-pressure X-ray photoelectron spectroscopy at relative humidity (RH) values from 0% to approximately 45%. Water adsorbs at low RHs and continues to grow gradually up to ∼1% RH, probably forming hydroxyls. Water grows rapidly above 1% RH, indicative of the formation of a molecular water film. The molecular water film formed reaches more than one monolayer in thickness at 10% RH. We show that the energy separation between Ge4+ and Ge0+ signals in Ge3d spectra increases with RH until it reaches 1%. In addition, the collapse of an initial abrupt GeO2/Ge interface is demonstrated in this humidity range, indicating that water molecules in the gas phase infiltrate into the permeable GeO2 film, and water-related species accumulate at the GeO2/Ge interface. We propose that water-related species emit electrons to the Ge bulk and positive charges are created in GeO2 close to the...

Insight into unusual impurity absorbability of GeO2 in GeO2/Ge stacks

Adsorbed species and its diffusion behaviors in GeO(2)∕Ge stacks, which are future alternative metal-oxide-semiconductor (MOS) materials, have been investigated using various physical analyses. We clarified that GeO(2) rapidly absorbs moisture in air just after its exposure. After the absorbed moisture in GeO(2) reaches a certain limit, the GeO(2) starts to absorb some organic molecules, which is accompanied by a structural change in GeO(2) to form a partial carbonate or hydroxide. We also found that the hydrogen distribution in GeO(2) shows intrinsic characteristics, indicative of different diffusion behaviors at the surface and at the GeO(2)∕Ge interface. Because the impurity absorbability of GeO(2) has a great influence on the electrical properties in Ge-MOS devices, these results provide valuable information in realizing high quality GeO(2)∕Ge stacks for the actual use of Ge-MOS technologies.

Control of Interfacial Properties of Al2O3/Ge Gate Stack Structure Using Radical Nitridation Technique

We have investigated the control of the interfacial properties of Al2O3/Ge gate stack structures by the radical nitridation technique. In the Al2O3/Ge structures formed by the atomic layer deposition method, the interface state density increases with the deposition temperature due to the decrease in the thickness of the Ge oxide interlayer. On the other hand, the hysteresis width of the capacitance–voltage (C–V) characteristics decreases with increasing deposition temperature, which indicates a decrease in the oxide trap density near the interface. We also investigated the control of the interfacial structure by the radical nitridation of Al2O3/Ge to form an interfacial structure after the deposition of a high-k dielectric layer. The results of X-ray photoelectron spectroscopy reveal that an Al2O3/Ge3N4/GeO2/Ge stack structure is formed after the radical nitridation owing to the minimal oxygen diffusion into the Al2O3/Ge interface. Furthermore, the interfacial mixing is suppressed after radical nitridation at less than 300 °C. As a result, we can decrease the interface state density of the Al2O3/Ge sample after the radical nitridation by more than one order of magnitude compared with that without radical nitridation.

Effect of high-pressure H2O treatment on elimination of interfacial GeOX layer between ZrO2 and Ge stack

This investigation demonstrates the effect of high-pressure H2O treatment on the elimination of the interfacial germanium suboxide (GeOX) layer between ZrO2 and Ge. The formation of GeOX interlayer increases the gate-leakage current and worsen the controllability of the gate during deposition or thermal cycles. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy reveal that high-pressure H2O treatment eliminates the interfacial GeOX layer. The physical mechanism involves the oxidation of non-oxidized Zr with H2O and the reduction of GeOX by H2. Treatment with H2O reduces the gate-leakage current of a ZrO2/Ge capacitor by a factor of 1000.

Fabrication of High- κ /Ge Stacks with High Quality GeO2 Interlayer

not Available.

Evaluation of GeO desorption behavior in the metalGeO(2)Ge structure and its improvement of the electrical characteristics.

The relation between germanium monoxide (GeO) desorption and either improvement or deterioration in electrical characteristics of metalGeO(2)Ge capacitors fabricated by thermal oxidation has been investigated. In the metalGeO(2)Ge stack, two processes of GeO desorption at different sites and at different temperatures were observed by thermal desorption spectroscopy measurements. The electrical characteristics of as-oxidized metalGeO(2)Ge capacitors shows a large flat-band voltage shift and minority carrier generation due to the GeO desorption from the GeO(2)Ge interface during oxidation of Ge substrates. On the other hand, the electrical properties were drastically improved by a postmetallization annealing at low temperature resulting in a metal catalyzed GeO desorption from the top interface.

GeOx interface layer reduction upon Al-gate deposition on a HfO2∕GeOx∕Ge(001) stack

The metallization of HfO2∕Ge by Al at room temperature was studied using photoemission and inverse photoemission. Upon deposition, Al reduces the GeOx interfacial layer between Ge and HfO2, and a thin Al2O3 layer is formed at the Al∕HfO2 interface. The band alignment across the Al∕HfO2∕Ge stacks is also addressed.

Cluster self-organization of TR-containing germanate systems: Suprapolyhedral precursors and self-assembly of the crystal structures of the LiNdGeO4 and CeGeO4 compounds

A combinatorial-topological analysis of the orthogermanates LiNdGeO4 (space group Pbcn) and CeGeO4 (space group I 41/a, the scheelite structure type), which have MT frameworks composed of polyhedral structural units in the form of M dodecahedra (NdO8 and CeO8) and T tetrahedra (GeO4), is performed using the method of coordination sequences with the TOPOS program package. It is established that the structures of both orthogermanates are characterized by equivalent crystal-forming nets 4444. The cluster precursors of the M 2 T 2 cyclic type are identified by the method of two-color decomposition. The local symmetry of four-polyhedral clusters corresponds to the point group 2. In the precursor of the LiNdGeO4 orthogermanate, the Li atom is located above the M 2 T 2 ring. The number of Li-O bonds in this precursor is 4. The cluster precursors M 2 T 2 and LiM 2 T 2 are responsible for the formation of crystal-forming clusters of a higher level according to the mechanism of matrix self-assembly. The coordination numbers of the cluster precursors in two-dimensional nets for these structures are found to be equal to 4. The equivalent bilayer TR,Ge stacks that consist of eight cluster precursors are revealed in the structures under investigation. It is demonstrated that there exist three types of translational interlayer arrangements of cluster precursors upon the formation of macrostructures of the orthogermanates.