Ge nFETs Research Articles

Understanding and Controlling Band Alignment at the Metal/Germanium Interface for Future Electric Devices

Germanium (Ge) is a promising semiconductor as an alternative channel material to enhance performance in scaled silicon (Si) field-effect transistor (FET) devices. The gate stack of Ge FETs has been much improved based on extensive research thus far, demonstrating that the performance of Ge FETs is much superior to that of Si FETs in terms of the on-state current. However, to suppress the performance degradation due to parasitic contact resistance at the metal/Ge interface in advanced nodes, the reduction of the Schottky barrier height (SBH) at the metal/Ge interface is indispensable, yet the SBH at the common metal/Ge interface is difficult to control by the work function of metal due to strong Fermi level pinning (FLP) close to the valence band edge of Ge. However, the strong FLP could be alleviated by an ultrathin interface layer or a low free-electron-density metal, which makes it possible to lower the SBH for the conduction band edge of Ge to less than 0.3 eV. The FLP alleviation is reasonably understandable by weakening the intrinsic metal-induced gap states at the metal/Ge interface and might be a key solution for designing scaled Ge n-FETs.

On-Current Enhancement in TreeFET by Combining Vertically Stacked Nanosheets and Interbridges

The TreeFET channel, which is a combination of vertically stacked nanosheet channels and fin-shaped interbridge channels in between the nanosheets, can provide an additional channel conduction area to improve the on-current without increasing the device footprint. To provide on-current enhancement, a minimum height is required for the interbridge that is dependent on the width of the interbridge and the physical gate oxide thickness. Minimizing the threshold voltage difference between the interbridges and the nanosheet channels also plays a crucial role in the optimization of the on-current of TreeFETs. The design criteria for TreeFETs are studied using TCAD simulation of Ge nFETs.

(Invited) Epitaxial Ge/GeSn High Mobility Channel Transistors

To boost the drive current of transistor and/or reduce power consumption, new channel materials with high carrier mobility such as SiGe/Ge/GeSn have been considered as the promising candidates for the continuous scaling of Moore’s law. SiGe channel have been used in the industry for pFETs, and the addition of Sn into Ge to further enhance the hole mobility is the attractive area of research. The strained GeSn on Ge/Si grown by CVD provides higher hole mobility than Ge due to the biaxial compressive strain and effective mass reduction by Sn incorporation. To ensure the gate stack quality, and reduce the scattering of holes in the GeSn channel by oxide/interface charges and surface roughness, the epitaxy Ge cap with significant ΔEV has been integrated. The Ge-cap/GeSn/Ge quantum well structure with [Sn] up to 9% is grown by CVD on SOI, and the low temperature process is used to fabricate the devices without Sn segregation/diffusion. By optimizing the cap thickness and thermal budget of gate stack formation, the high mobility (~430cm2/V-s) of the CVD-grown GeSn quantum well p-MOSFETs is achieved to demonstrate the possible integration of GeSn material in industrial fabrication. The high hole mobility and reduced low frequency noise are obtained using quantum well structures with optimal cap thickness of 1 nm. The Ge cap also reduces the defects formed by Sn diffusion into dielectric. To improve the gate controllability and increase drive current with same footprint, the gate-all-around (GAA) pFETs using GeSn channels will be reported. For Ge nFETs, junctionless GAAFETs with high drive current and high Ion/Ioff are investigated. To boost the drive current and to suppress short channel effects, the optimized doping profile is needed. Since the subthreshold characteristic of JL FET is highly related to the channel cross-section and channel doping, the channel doping of 1.2x1019cm-3 is used. However, it is too low for the S/D region, and heavily doped Ge (~1.2x1020 cm-3) is used in S/D by selective laser annealing with NiGe contact to reduce the parasitic resistance. The optimized doping profile is achieved by selective laser annealing in the S/D, with Pt as hard mask on channel region to reflect the laser light in the channel. The demonstrated Ge JL nGAAFET with fin width (Wfin) down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/μm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. Note that the increasing mobility with increasing temperature indicates the impurity scattering is dominant. With Ge/GeSn CVD growth and optimized process, GAA transistors with high mobility channels can be realized as promising candidates for future CMOS scaling.

Temperature and field dependent low frequency noise characterization of Ge n-FETs

We report temperature (RT-150 K) and field dependent low frequency noise measurements on Ge n-FETs. Specifically, we delineate the temperature, field, and interfacial layer (GeON vs. GeO2) dependence of the gate overdrive index (β) on corresponding changes in volume interface trap density (Nit) and mobility (μ). For Nit < 1 × 1020 cm−3 eV−1, the dominant noise mechanism, number or mobility fluctuation, depends on the change in μ, but for Nit > 1 × 1020 cm−3eV−1 near the conduction band edge, changes in μ as well as Nit determine the noise mechanism. Finally, we show that the β values of Ge n-FETs are significantly different from conventional Si transistors as well as Ge p-FETs at RT and 150 K due to much higher Nit and/or μ values of the Ge n-FETs.

Ultimate Performance Projection of Ultrathin Body Transistor Based on Group IV, III-V, and 2-D-Materials

We report the ultimate performance of a double-gate ultrathin body (DG-UTB) FET employing materials from group IV, III-V, and 2-D materials based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high-performance (HP) and low-power (LP) technologies. The band structures of the channel materials were obtained using the sp $^{3}\text{d}^{5}\text{s}^{\ast }$ tight binding model and the first-principles density functional theory. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The leakage current due to direct source-to-drain tunneling was calculated based on Wentzel–Kramers–Brillouin approximation. For nFET used in the HP technology, GaSb nFET has the best voltage scalability followed by Ge nFET in 2026. It was found that $I_{\mathrm{\scriptscriptstyle ON}}$ of InAs and In0.3 Ga0.7Sb nFETs is among the lowest, and they require larger power supply voltage ( $V_{\mathrm{DD}}$ ) among III-V semiconductors considered to achieve $I_{\mathrm{\scriptscriptstyle ON}}$ of silicon nFET. However, they show lower power delay product (PDP) due to their smaller electron effective mass, resulting in higher carrier velocity. Ge pFET offers the best voltage scalability for pFET used in the HP technology. For the voltage scalability assessment based on the requirements for the LP technology, MOSFETs based on Si offer better performance in terms of $I_{\mathrm{\scriptscriptstyle ON}}$ and PDP than MOSFETs based on 2-D materials. Among the 2-D materials studied, black phosphorus and silicane MOSFETs exhibit higher $I_{\mathrm{\scriptscriptstyle ON}}$ and better voltage scalability and PDP.

High Electron Mobility n-Channel Ge MOSFETs with Sub-Nm EOT

1. Introduction The demonstration of high electron mobility in Ge n-MOSFETs is not an easy task due to unknown carrier scatterings in Ge inversion channel. The first step to clear the big hurdle is to improve the peak electron mobility by reducing the interface states density (Dit ). We have succeeded in the reduction of Dit (<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 oxidation (HPO) [1, 2]. However, there still remain two critical challenges. One is how to suppress the significant degradation of high-Ns electron mobility (Ns: carrier density). The other one is how to keep high electron mobility in the thin EOT region [3]. Those two are of paramount importance for pushing Ge CMOS in the real technology. 2. Reinvestigation of High-Ns Electron Mobility Coulomb scattering, phonon scattering, and surface roughness scattering are generally considered in MOS inversion layer. By employing HPO, Coulomb scattering has been dramatically reduced, resulting that the peak electron mobility in Ge n-FET is now x2.5 higher than that in Si case [1]. On the other hand, high-Nselectron mobility is generally understood from the interface roughness scattering. Here, not only the roughness height but also the roughness correlation length should be considered, according to the conventional roughness scattering theory [4, 5]. First, we have challenged to realize the atomically flat Ge (111) surface by using H2annealing [6] to reduce the roughness correlation length.Next, it is discussed how the atomically flat surface is affected by the oxidation. The results show that the step and terrace structure is maintained by selecting the temperature under a high-pressure oxidation [7].Then, excellent high-Nselectron mobility has been demonstrated. 3. EOT Reduction Recently we have newly found two facts to breakthrough this challenge. The first one is that the low temperature HPO reduces the oxidation rate [8]. This fact enables us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. The other one is to replace HPO-GeO2 with high-k oxides which are thermodynamically appropriate for Ge. This means that we can use low oxygen potential oxides instead of HPO- GeO2. Then, we have reached a conclusion that Y2O3 is one of the best candidates on Ge [9]. This material is actually what we have regarded as the Ge-friendly insulator for Ge gate stacks previously from experimental viewpoint [10]. Our recent results have shown that Y2O3-doped GeO2 (YGO) is better than pure Y2O3 on Ge [11]. The resultant electron effective mobility in Ge n-FETs at Ns=1013cm-2is significantly improved down to sub-nm EOT region. Conclusion We can engineer the Ge interface through understanding both of thermodynamics in gate stack formation and of kinetics in surface planarization and oxidation. Thus, it is concluded that Ge CMOS is quite promising. Acknowledgements This work was partly supported by Grant-in-Aid for Scientific Research (A) by Japan Society for the Promotion of Science (JSPS), and by the JSPS Core-to-Core Program “International Collaborative Research Center on Atomically Controlled Processing for Ultra-large Scale Integration” References [1] C. H. Lee et al., TED-58(2011)1295.[2] K. Nagashio et al., MRS Symp. Proc. 1155(2009) C06-02.[3] M. Caymax et al., IEDM 2009-461.[4] Y. Matsumoto and Y. Uemura, JJAP Suppl. 2(1974) 367.[5] C. H. Lee et al., JJAP 51(2012)104203.[6] T. Nishimura et al., APEX 5(2012)121301.[7] C. H. Lee et al., IEDM 2013-32.[8] C. H. Lee et al., APEX 5 (2012)114001.[9] C. H. Lee et al., IEDM 2013-40.[10]A. Toriumi et al., “Advanced Gate Stacks for High-Mobility Semiconductors", pp. 257-267 (2007, Springer).[11] C. Lu et al., APL. 104 (2014) 092909.