Gbps Transceiver Research Articles

A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System

A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System

Trigger Merging Module for the J-PARC E16 Experiment

An experiment to measure an invariant mass of {\phi} mesons in nuclear medium is planned as the J-PARC E16 experiment. A trigger merging module (TRG-MRG) has been developed to detect leading-edges from 256 channels of discriminator-output signals and transmit those serialized hit data to trigger decision module with four optical links. The result of the test shows enough performance of the TRG-MRG as 1 ns TDC and data multiplexer with four 6.25 Gbps transceivers.

General Purpose Readout Board $\pi$ LUP: Overview and Results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.

(Invited) Ge Photodiodes for CMOS Photonics Optical Engines and Interconnects

In this contribution the CMOS photonics technology developed and commercialized by Luxtera (LuxG) is reviewed with particular emphasis on the Ge integrated photodiodes. The advantages of integration and usage of standard CMOS foundry toolset/processes/practices are discussed with details of the newest 14Gbps (FDR) and 25Gbps (EDR) transceiver chips.