Gate Voltage Vg Research Articles

Photoconductance of aligned SnO2 nanowire field effect transistors

We report on the optoelectronic properties of the aligned SnO2 nanowire (NW) field effect transistors (FETs) fabricated via a sliding transfer of NWs grown by chemical vapor deposition. Photocurrent measurements with polarized UV light confirmed a well aligned NWs along the channels. UV photosensitivity of ∼107 at the gate voltage Vg=−40 V was obtained due to a small dark-current at the turn-off state of FET. The dynamic response of the photocurrent became faster for the higher mobility SnO2 NW FETs. We expect our aligned SnO2 NW FETs will be useful as polarized UV detectors with a high sensitivity.

Renormalization of the phonon spectrum in semiconducting single-walled carbon nanotubes studied by Raman spectroscopy

In situ Raman experiments together with transport measurements have been carried out in single-walled carbon nanotubes as a function of electrochemical top gate voltage (Vg). We have used the green laser (EL=2.41 eV), where the semiconducting nanotubes of diameter ~1.4 nm are in resonance condition. In semiconducting nanotubes, the G−- and G+-mode frequencies increase by ~10 cm−1 for hole doping, the frequency shift of the G− mode is larger compared to the G+ mode at the same gate voltage. However, for electron doping the shifts are much smaller: G− upshifts by only ~2 cm−1 whereas the G+ does not shift. The transport measurements are used to quantify the Fermi-energy shift (EF) as a function of the gate voltage. The electron-hole asymmetry in G− and G+ modes is quantitatively explained using nonadiabatic effects together with lattice relaxation contribution. The electron-phonon coupling matrix elements of transverse-optic (G−) and longitudinal-optic (G+) modes explain why the G− mode is more blueshifted compared to the G+ mode at the same Vg. The D and 2D bands have different doping dependence compared to the G+ and G− bands. There is a large downshift in the frequency of the 2D band (~18 cm−1) and D (~10 cm−1) band for electron doping, whereas the 2D band remains constant for the hole doping but D upshifts by ~8 cm−1. The doping dependence of the overtone of the G bands (2G bands) shows behavior similar to the dependence of the G+ and G− bands.

Near-surface nanoscale InAs Hall cross sensitivity to localized magnetic and electricfields

We have measured the room temperature response of nanoscale semiconductor Hallcrosses to local applied magnetic fields under various local electric gate conditionsusing scanning probe microscopy. Near-surface quantum wells of AlSb/InAs/AlSb,located just 5 nm from the heterostructure surface, allow very high sensitivity tolocalized electric and magnetic fields applied near the device surfaces. The Hallcrosses have critical dimensions of 400 and 100 nm, while the mean free path ofthe carriers is about 160 nm; hence the devices nominally span the transitionfrom diffusive to quasi-ballistic transport. With certain small gate voltages (Vg) the devices of both sizes are strongly responsive to the local magnetic field at the centerof the cross, and the results are well described using finite element modeling. At highVg, the response to local magnetic fields is greatly distorted by strong electric fields appliednear the cross corners. However we observe no change in behavior with the size of thedevice.

Fabrication of field-effect transistors based on Fe3+-doped titania by sol–gel methods

TiO2-based field-effect transistors (FETs) were designed and fabricated using nano-TiO2 and Fe3+-doped TiO2 samples prepared by sol–gel methods. Homo-junction characteristics of nano-TiO2/Fe3+-doped TiO2 films, which perform as a semiconductor diode, were analyzed by current–voltage (I–V) data. Two designs of the metal–semiconductor field effect transistors (MESFETs), back and front gate cases, were fabricated and characterized by I–V measurements. The FET devices were evaluated by analyzing the data of source-drain current versus voltage (Ids–Vds) which are controlled by the gate voltage (Vg). In addition, the effects of the junction diode behavior on the transistor were discussed according to the energy band diagrams of TiO2 and Fe3+-doped TiO2 semiconductors.

The formation of bound states and the conductance modulation on 0.7 anomaly in a quantum wire

The electron transport in a short quasi-1D quantum wire is studied. In addition to the conductance quantization, several resonances are observed. Two of the resonances appear as extra plateaus below 2e2/h. A gate voltage offset is used to tune the local potential of the quantum wire. A robust resonance is seen and the resonances evolve continuously with respect to the offset. The conductance has opposite responses to temperature in successive regions of gate voltage Vg. In the source-drain bias spectroscopy, two more conductance peaks are observed in addition to the Zero-Bias-Anomaly. The locations of the extra peaks evolve with respect to Vg showing a pattern similar to that in a quantum dot. We suggest that a bound state forms in the quantum wire. The prominent 0.7 anomaly in our quantum wire is recognized as the residue of conductance resonance.

Numerical study of Coulomb oscillation and phase shift through quantum dots in a magnetic field

Coulomb oscillation and phase shift are examined numerically through semiconductor quantum dots in a magnetic field. A realistic shape of the quantum dot, tunnel barriers and leads is modeled using a quasi-one-dimensional tight-binding model with smooth potential barriers. In the absence of magnetic field, we obtain a peak structure of the conductance as a function of gate voltage Vg (Coulomb oscillation) with a sequence of abrupt change of the transmission phase, so-called phase lapse. This agrees with experimental results. The magnetic field removes the phase lapse. The phase shift changes continuously, either increases or decreases by almost π with an increase in Vg, reflecting complex wavefunctions at the Fermi level.

FinFET reliability study by forward gated-diode generation–recombination current

Reliability of FinFETs is studied in this paper using the forward gated-diode generation–recombination (G–R) current. The current–voltage characteristics of a FinFET are measured for parameter extraction and a mathematical algorithm is used to extract the stress-induced interface states and oxide traps of the FinFET from the G–R current measurement. It is observed that the stress-induced interface states and oxide traps can be distinguished by observing the shift of the peak G–R current in the body current (Ib) versus gate voltage (Vg) characteristic. The interface states cause a change in the maximum G–R current (ΔIpeak) while the oxide traps result in a shift of the gate voltage (ΔVg) corresponding to the ΔIpeak. Unlike bulk MOSFETs, the dominant degradation mechanism of FinFETs is found to be the oxide traps formation rather than the interface states generation.

Anomalous Hot-Carrier-Induced Increase in Saturation-Region Drain Current in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

Anomalous increase in saturation-region drain current Id(sat) but serious on-resistance degradation (decrease in linear-region drain current) is observed in n-type high-voltage lateral diffused MOS transistors stressed under medium gate voltage Vg. However, Id(sat) is degraded for the devices stressed under low and high Vg. Experimental data reveal that two competing mechanisms are responsible for the shift of Id(sat). One is the interface state Nit formation in the N- drift region. The other is the Nit formation in the channel region. The former mechanism leads to the anomalous increase in Id(sat), whereas the latter mechanism causes the to decrease. Experimental data and technology computer-aided-design simulations confirm that the impact ionization rate of the device is enhanced if significant Nit formation in the N- drift region is present. According to the results presented in this paper, significant formation in the drift region is identified to be the main mechanism responsible for the anomalous increase in Id(sat).

Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion

In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1dB compression point.

Effect of Gate Voltage on Hot-Carrier-Induced On-Resistance Degradation in High-Voltage n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

The phenomenon and mechanism of hot-carrier-induced on-resistance (Ron) degradation for the n-type lateral diffused metal–oxide–semiconductor (MOS) transistors stressed under various gate voltages (Vg) are investigated. Ron degradation of the device is found to be attributed to the interface state (Nit) generation in the N- drift region. Moreover, Ron degradation is almost identical for the devices stressed under medium Vg and high Vg, despite the fact that bulk current of the device is much greater at high Vg bias. Such an anomalous Ron degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and Nit generation efficiency.

Huge positive magnetoresistance in a gated AlGaAs∕GaAs high electron mobility transistor structure at high temperatures

Magnetoresistivity measurements on a gated AlGaAs∕GaAs high electron mobility transistor (HEMT) structure were performed at high temperatures T. By changing the applied gate voltage Vg, we can investigate the observed huge positive magnetoresistance (PMR) at different effective disorder and density inhomogeneity within the same HEMT structure. The observed PMR value increases with increasing disorder in the depletion mode (Vg⩽0). Moreover, the PMR value is not limited by the quality of the HEMT structure at T=80K. Such results pave the way for low-cost, high-throughput GaAs-based HEMT fabrication for future magnetic sensing and recording devices fully compatible with the mature HEMT technology.

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (Vg = Vd), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously (concurrent HCI-NBTI), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under Vg = Vd at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under Vg = Vd shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.

Research on metastable electron traps in the modified SOI materials induced by Si ion implantation

Silicon-On-Insulator (SOI) materials were modified by Si ion implantation with different doses, as reported in this letter. The electrical performance was studied and the effect of a modification technique on the SOI materials was investigated. The characteristic, obtained by pseudo-metal-oxide-semiconductor (pseudo-MOS) method, showed that the drain ID current versus gate voltage VG(ID−VG) curves shifted along the axis of VG with the change of Si ion implantation doses. The results of electron paramagnetic resonance (EPR), x-ray photoelectron spectroscopy (XPS), and electronic test suggested that the parameters of implantation affect the electrical performance and that the metastable electron traps are introduced into the buried oxide layers of SOI materials.

Taylor expansions of band-bending in MOS capacitance: application to scanning capacitance microscopy

The differential capacitance C(Vg) = dQM/dVg in a metal-oxide-semiconductor structure introduces the silicon capacitance Cs(ΨS) = −dQS/dΨS depending on the surface band-bending ΨS at the oxide–semiconductor interface. In order to calculate the dependence of Cs on the gate voltage Vg, we propose in this paper a simple numerical method, based on first-order Taylor expansions, to inverse the explicit equation Vg = f(ΨS). This method is then applied to calculate the analytic differential capacitance of the scanning capacitance microscope (SCM) in all conditions relative to physical parameters of SCM such as oxide thickness, doping profiles and probe erosion. It results in a competitive tool for SCM users to evaluate the theoretical values of capacitance and differential capacitance in all configurations.

Field-effect modulation of contact resistance between carbon nanotubes

Local transport properties of a carbon nanotube (CNT) thin-film transistor (TFT) have been investigated by conducting atomic force microscopy. The current in a CNT bundle is almost constant, whereas it drastically decreases at the contacts between CNTs. Current drops at the contacts are reduced with increasing negative gate voltage VG. The results show that the contact resistance between CNTs can be modified by VG, and the operation of CNT-TFT is mainly governed by the modulation of contact resistance.

Breakdown of the adiabatic Born–Oppenheimer approximation in graphene

The adiabatic Born-Oppenheimer approximation (ABO) has been the standard ansatz to describe the interaction between electrons and nuclei since the early days of quantum mechanics. ABO assumes that the lighter electrons adjust adiabatically to the motion of the heavier nuclei, remaining at any time in their instantaneous ground state. ABO is well justified when the energy gap between ground and excited electronic states is larger than the energy scale of the nuclear motion. In metals, the gap is zero and phenomena beyond ABO (such as phonon-mediated superconductivity or phonon-induced renormalization of the electronic properties) occur. The use of ABO to describe lattice motion in metals is, therefore, questionable. In spite of this, ABO has proved effective for the accurate determination of chemical reactions, molecular dynamics and phonon frequencies in a wide range of metallic systems. Here, we show that ABO fails in graphene. Graphene, recently discovered in the free state, is a zero-bandgap semiconductor that becomes a metal if the Fermi energy is tuned applying a gate voltage, Vg. This induces a stiffening of the Raman G peak that cannot be described within ABO.

Single-Electron Transport Driven by Surface Acoustic Waves: Moving Quantum Dots Versus Short Barriers

We have investigated the response of the acoustoelectric current driven by a surface-acoustic wave through a quantum point contact in the closed-channel regime. Under proper conditions, the current develops plateaus at integer multiples of ef when the frequency f of the surface-acoustic wave or the gate voltage Vg of the point contact is varied. A pronounced 1.1 MHz beat period of the current indicates that the interference of the surface-acoustic wave with reflected waves matters. This is supported by the results obtained after a second independent beam of surface-acoustic wave was added, traveling in opposite direction. We have found that two sub-intervals can be distinguished within the 1.1 MHz modulation period, where two different sets of plateaus dominate the acoustoelectric-current versus gate-voltage characteristics. In some cases, both types of quantized steps appeared simultaneously, though at different current values, as if they were superposed on each other. Their presence could result from two independent quantization mechanisms for the acoustoelectric current. We point out that short potential barriers determining the properties of our nominally long constrictions could lead to an additional quantization mechanism, independent from those described in the standard model of 'moving quantum dots'.

Vox/Eox-Driven Breakdown of Ultrathin SiON Gate Dielectrics in p-Type Metal Oxide Semiconductor Field Effect Transistors under Low-Voltage Inversion Stress

The breakdown mechanism of ultrathin SiON gate dielectrics in p-type metal oxide semiconductor field effect transistors having p+gates (p+gate-pMOSFETs) has been studied. Systematic study with varying gate doping concentrations has revealed that, in the case of p+gate-pMOSFET in inversion mode, gate dielectric breakdown under stress voltage lower than -4 V is driven by oxide voltage (Vox) or oxide field (Eox), while the breakdown under stress voltage higher than -4 V is driven by gate voltage (Vg). The Vox/Eox-driven breakdown observed under low stress voltage is quite important to the reliability of low-voltage complementary metal oxide semiconductor (CMOS). By studying the mechanism of the breakdown, it has been clarified that the breakdown is not induced by electron current. The concept that the breakdown is due to same mechanism as the negative bias temperature instability (NBTI), namely the interfacial hydrogen release driven by Eox, has been shown to be possible. However, direct tunneling of holes driven by Vox has also been found to be a possible driving force of the breakdown. Although a decisive conclusion concerning the mechanism issue has not yet been obtained, the key factor that governs the breakdown has been shown to be Vox or Eox.

700-V 1.0-$hboxmOmega cdot hboxcm^2$Buried Gate SiC-SIT (SiC-BGSIT)

Ultralow on-resistance silicon carbide static induction transistors with buried gate structures (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicrometer buried p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> gate structure was fabricated by the combination of submicrometer trench dry etching and epitaxial growth on a trench structure. The breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> and specific on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onS</sub> of the fabricated SiC-BGSIT were 700 V at a gate voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =-12V, and 1.0 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a current density J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> =200A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =2.5V, respectively. This R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onS</sub> is the lowest on-resistance for ~600 V class power switching devices, including other SiC devices and GaN HEMTs

Temperature-Dependent Gate Effect of Sintered HgTe Nanoparticles

In this study, the electronic properties of sintered HgTe nanoparticles are characterized to determine the type of charge carrier within them, and to investigate their gate effects as a function of temperature. HgTe nanoparticles synthesized by the colloidal method were first deposited on thermally oxidized Si substrates by spin-coating, and then sintered at 150 °C. The sintered nanoparticles were determined to be p-type by analyzing the drain current and drain–source voltage (Id–Vds) relationship as a function of the gate voltage (Vg). The field-effect mobilities of the holes in the sintered HgTe nanoparticles are estimated to be 0.041, 0.036, and 0.022 cm2/(V·s) at 60, 180, and 300 K, respectively. The variation in the slope of the Id–Vds curve as a function of Vg becomes more distinctive as temperature decreases. At temperatures lower than 140 K, an inversion mode was observed for the channel of the sintered nanoparticles.