Gate Leakage Current Decreases Research Articles

Gate leakage mechanisms of the AlGaN/GaN HEMT with fluorinated graphene passivation

The AlGaN/GaN high-electron-mobility transistor (HEMT) passivated by fluorinated graphene (FG) has been investigated. The performances of the HEMTs without passivation before and after F plasma treatment, with FG, Silicon nitride (SiNx), FG/SiNx passivation were contrasted. Compared with the HEMT without F plasma treatment and passivation, the gate leakage current decreases one and a half orders of magnitude after F plasma treatment and SiNx passivated, and four orders of magnitude after FG and FG/SiNx passivated. To study the leakage mechanisms, the temperature dependences of gate leakages have been tested at 323 K–473 K. Through analysis and fitting, the leakages are composed of three components, which are thermionic emission (TE) current, two-dimensional variable range hopping (2D-VRH) current, and Fowler–Nordheim tunneling (FNT) current. TE dominates in the high forward bias region. 2D-VRH dominates in low forward bias. And the chief leakage mechanisms at reverse bias are 2D-VRH and FNT. At 473 K, Schottky barrier height of the HEMT with FG passivation is 1.21 eV. The activation energy and the effective barrier height on the HEMT with FG passivation are 0.64 eV and 0.33 eV respectively. Furthermore, the reasons for the decrement of the gate leakage on the HEMT with FG and FG/SiNx passivation are the enhancement of Schottky barrier heights and augmentation of activation energy. And the improvement in gate leakages for the HEMT passivated by FG/SiNx mainly results from the effect of FG.

Proton irradiation impact on interface traps under Schottky contact in AlGaN/GaN heterostructure

The effect of 3 MeV proton irradiation on interface traps under a Schottky contact in an AlGaN/GaN heterostructure has been investigated in this work. Utilizing the frequency-dependent conductance technique, the detailed information about interface traps under different proton doses has been evaluated. When the proton irradiation dose is increased to 5 × 1014 H+/cm2, it is observed that the deepest energy level of interface traps changes from 0.375 eV to 0.346 eV and the shallowest energy level changes from 0.284 eV to 0.238 eV. The corresponding energy range expands from 0.091 eV to 0.108 eV. Especially, the trap density at the deepest energy level and that at the shallowest energy level are reduced by 65% and 93%, respectively. Transmission electron microscopy and energy dispersive x-ray spectroscopy are also used to assess the Schottky contact interface, and no element inter-diffusion is observed after proton irradiation. The reverse gate leakage current decreases with an increase in the proton irradiation dose, which agrees with the reduction in interface trap density.

A low-temperature supercritical nitridation technology for enhancing the performance of AlGaN/GaN HEMTs

A non-destructive low-temperature supercritical nitridation (LTSCN) is proved to boost the performance of AlGaN/GaN HEMTs. The samples were treated at 120 ℃ in a supercritical CO2 fluid mixed with NH3 under 20.7 MPa for one hour. After the LTSCN, the gate leakage current decreases by 69.6 % for an increase of the Schottky barrier height and the subthreshold swing is reduced by 19.9 %. Furthermore, the on-resistance is reduced by 20.4 % due to an enhancement of the mobility. The slow trap state density near AlGaN/GaN interface decreases from (5.12×1013 to 7.07×1013) cm−2·eV−1 to (1.80×1013 to 2.36×1013) cm−2·eV−1 with a decrease in activation energy from (0.492 to 0.500) eV to (0.467 to 0.496) eV after the LTSCN. A modified model of the LTSCN is presented to expound the change of the slow traps and the Coulomb scattering effect of electrons capture in the changed slow traps is adopted to explain the mobility improvement.

Positive temperature dependence of time-dependent breakdown of GaN-on-Si E-mode HEMTs under positive gate stress

We report an extensive analysis of the time-dependent breakdown of E-mode GaN-on-Si power HEMTs subjected to positive gate stress and demonstrate that TTF (time-to-failure) has a positive temperature dependence. The analyzed devices have a p-type gate; large (60 A) power transistors were subjected to positive stress at different voltages and temperatures ranging from 25 °C to 250 °C. The original results collected in this paper demonstrate that (i) constant voltage stress induces a gradual decrease in gate leakage current, which is ascribed to hole-trapping in Mg-acceptors located at the p-GaN/AlGaN interface; (ii) this trapping process becomes less pronounced at high temperatures, due to a faster detrapping from the shallow Mg-related traps; (iii) the devices stressed at the same voltage and different temperatures show a similar initial gate leakage, due to the fact that in the analyzed regime, gate conduction is dominated by Fowler-Nordheim tunneling, a field-related, rather than thermally activated, process; (iv) the time-to-failure has a positive temperature dependence. The latter result is explained by considering that time-dependent breakdown occurs due to the accumulation of positive charges at the p-GaN/AlGaN interface, which results in an increased injection of 2DEG electrons into the p-GaN layer, where they are accelerated by the electric field. High temperatures favor the detrapping of holes, thus reducing this process and leading to a better stability.

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

Recently, III-V materials have attracted great interest among researchers in exploring the substitution of the Si channel in scaled logic field-effect transistors [1]. To enhance mobility and speed, High Electron Mobility Transistors (HEMTs) are being experimented with III-V materials. As a result, different material systems for HEMTs are appearing. InAs/AlSb HEMTs have appeared as a promising device as it has electron mobility as high as 30000 cm2/Vs, fT and fMAX exceeding 230 GHz [2]. However, technological limitations are the low breakdown voltage associated with the narrow bandgap of the InAs channel and additional gate leakage current due to staggered band alignment at the InAs/AlSb heterojunction. Recently high breakdown field of 5MV/cm and reduced gate leakage current of e-beam evaporated Al2O3on top of conventional InAs/AlSb HEMT structure has been reported experimentally by H. K. Lin et al [3]. But a complete self-consistent study and gate leakage current analysis of this device are yet to be done. In this work, we have performed a complete study of Capacitance-Voltage (CV) characteristics and Direct Tunneling (DT) gate leakage current using self-consistent Schrӧdinger-Poisson method in InAs/AlSb Metal-Oxide-Semiconductor HEMT (MOS-HEMT) by varying different process parameters as well as physical parameters like oxide thickness, channel thickness, capping layer composition, dielectric variation, delta doping concentration and temperature. We have investigated CV characteristics and DT gate leakage performance of the structure shown in figure 1 [3] by self-consistent simulation of 1-D coupled Schrӧdinger and Poisson equation [4]. We have used finite difference method for solving Poisson equation [5] and hamiltonian matrix formalism [6] for solving Schrӧdinger equation numerically. Strain effect is also incorporated in this simulator [7]. DT gate leakage current is obtained using the method where transmission probability is calculated using modified Wentzel–Kramers–Brillouin (WKB) method [8]. In our work, we have calculated transmission probability using transmission line analogy [9]. The conduction band diagram and carrier profile of the device obtained from the simulation are illustrated in figure 2. Figure 3 shows the CV characteristics for different channel thicknesses. There are two cross-over points in the curve which can be justified by the change of slope of sheet carried density with respect to the gate voltage. The gate leakage current decreases with channel thicknesses and this variation is shown in figure 4. This behavior can be explained by the upshift of eigen energies in the well as channel thickness is decreased which further causes reduction of transmission probability. CV characteristics are not affected by the change in dielectric material having same Equivalent Oxide Thickness (EOT) as shown in figure 5. However, gate leakage current is significantly reduced with the replacement of high-k HfO2 in place of Al2O3shown in figure 6. This can be justified by the fact that channel sheet carrier density remains same with the variation whereas gate leakage reduces due the reduction in transmission probability with the replacement of high-k dielectric. We have investigated CV characteristics and DT gate leakage current with self-consistent method for InAs/AlSb MOS-HEMT. We have observed that gate leakage current can be significantly reduced by using high-k dielectrics or thick channel layer. Our simulation work provides consistent trends of variations with the experiments [3] and shows how the performance of InAs/AlSb MOS-HEMT can be improved by varying appropriate physical/process parameters.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms.

Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors under reverse-bias stress

Impacts of SiN passivation on the degradation modes of AlGaN/GaN high electron mobility transistors are investigated. The gate leakage current decreases significantly upon removing the SiN layer and no clear critical voltage for the sudden degradation of the gate leakage current can be observed in the reverse-bias step-stress experiments. Gate-lag measurements reveal the decrease of the fast-state surface traps and the increase of slow-state traps after the passivation layer removal. It is postulated that consistent surface charging relieves the electric field peak on the gate edge, thus the inverse piezoelectric effect is shielded.

O2 /HMDSO-Plasma-Deposited Organic-Inorganic Hybrid Film for Gate Dielectric of MgZnO Thin-Film Transistor

An organic–inorganic hybrid film is deposited from O2/HMDSO plasma. The SiOSi/SiCH3 FTIR absorption ratio of this film increases with the process power and O2/HMDSO precursor flow ratio, resulting in a more inorganic-like film. This hybrid film is used as the gate dielectric of MgZnO TFTs. As the SiOSi/SiCH3 FTIR absorption ratio of the gate dielectric increases, the gate leakage current decreases, on/off current ratio increases, threshold voltage increases, and subthreshold swing increases. High SiCH3 bonding content in the gate dielectric improves TFT switching but deteriorates gate insulation, resulting in increased gate leakage current and decreased on/off current ratio.

MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

Ni-FUSI metal gate work function modulation technology

Through fabricating Ni-FUSI metal gate capacitors and analyzing their C-V and Vfb-EOT characteristics, it is found that Ga or Yb has more favorable modulation ability than conventional dopants. The work function of Ni-FUSI metal gate is modulated close to the top of valince band and the bottom of conduction band, which meets the requirement of high performance CMOS devices. The high modulation abilities of Ga and Yb are explained by dipole theory. Moreover, it is found that the capacitance value of Ni-FUSI metal gate capacitor increases after incorporating Ga or Yb into Ni-FUSI metal gate, but the gate leakage current decreases. And the detailed explanation for the above phenomena is also included in this article by analyzing C-V and gate leakage current characteristics.

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high- k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I– V curves are observed for Si 3N 4/SiO 2, Ta 2O 5/SiO 2, Ta 2O 5/SiO 2− y N y , Ta 2O 5/Si 3N 4, and TiO 2/SiO 2 stacked gates except for Al 2O 3/SiO 2 structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.