Gate-induced Drain Leakage Effects Research Articles

Anomalous GIDL Effect With Back Bias in FinFET: Physical Insights and Compact Modeling

In this work, we report a detailed study and modeling of bulk current in the low forward bias region. In the forward bias region, the bulk current shows a gate-induced drain leakage (GIDL) such as strong modulation with gate voltage although from the band alignment one would not expect any tunneling current. We propose physics-based modeling of this effect and derive a compact model for circuit simulators as state-of-the-art compact models are not suitable to capture this effect. The proposed model has been validated with measurement from Intel's bulk FinFET device.

Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect* *Project supported by the National Natural Science Foundation of China (Grant No. 61704130) and the Fund from the Science and Technology on Analog Integrated Circuit Laboratory, China (Grant No. JCKY2019210C029).

A novel n-type junctionless field-effect transistor (JLFET) with a step-gate-oxide (SGO) structure is proposed to suppress the gate-induced drain leakage (GIDL) effect and off-state current I off. Introducing a 6-nm-thick tunnel-gate-oxide and maintaining 3-nm-thick control-gate-oxide, lateral band-to-band tunneling (L-BTBT) width is enlarged and its tunneling probability is reduced at the channel--drain surface, leading the off-state current I off to decrease finally. Also, the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET, which could alleviate the capacitive load of the transistor in the circuit applications. Sentaurus simulation shows that I off of the new optimized JLFET reduced significantly with little impaction on its on-state current I on and threshold voltage V TH becoming less, thus showing an improved I on/I off ratio (5 × 104) and subthreshold swing (84 mV/dec), compared with the scenario of the normal JLFET. The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail, which could provide useful instruction for the device design.

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.

Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications

This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in order to improve the retention time: by the source/drain structure engineering or by applying a pulsed back gate bias.This work analyses the upgrade of the retention time by reducing the GIDL effect when the source/drain is underlapped with the gate.A lower retention time is observed for shorter channel length even optimizing the constant back gate bias, but the underlap devices present better results. The Gate-Induced Drain Leakage (GIDL), its amplification by a narrower base of the bipolar transistor inherent in the MOS structure and the longer effective channel length are the responsible mechanisms for the degradation of the retention time in both holding-0 and reading-0.The use of the pulsed back gate bias during write-1, as well as its variation, were analyzed. The pulsed bias case presents an improvement of 5% of the retention time and no difference was observed when the pulsed back gate level was varied.

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

The contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed. In order to fulfill this task, expressions for the leakage current due to carrier tunneling and GIDL effects at a Metal-Dielectric-Semiconductor structure were established and incorporated in the Symmetric Doped Double-Gate Model (SDDGM) for metal-oxide-semiconductor field-effect transistors (MOSFET). It is shown that both phenomena have to be taken into account for precise modeling of the device in all the operation regions although GIDL current can become predominant in the subthreshold region. The dependence of gate tunneling current in inversion and subthreshold regimes of operation is modeled as function of the applied voltages and transistor physical parameters by using analytical expressions. The present leakage current model is validated by comparing modeled with measured total gate and drain currents for FinFETs with different dimensions.

Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n/sup +/ and p/sup +/ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p/sup +/-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits.