Gate Fin Field-effect Transistor Research Articles

A 0.75V 10nm FinField-Effect Transistor Based Hybrid Self Controlled PreCharge Free Content Addressable Memory for Low Standby Power Applications

ABSTRACT The switching speed and driving capability have been enhanced by scaling the transistor size to nanoscale. The limitations in using MOSFET are that the short channel effects such as leakage current, subthreshold voltage, etc. thereby the Complementary Metal Oxide Semiconductor (CMOS) scaling is challenging now.This leads to the emergence of multi-gate devices, such as Fin Field Effect Transistor (FinFET) and Double Gate FinFET (DG-FinFET), which reduces the short channel effect. Now, a days memory plays a vital role in Integrated Circuits (IC), so the size of it must be scaled down to reduce the overall leakage andinstead of CMOS an advanced MOSFET such as FinFET can be used to avoid SCE. The area of the memory Static Random Access Memory (SRAM) is reduced by eliminating the two-load transistor. The novel 4T SRAM is designed at 10 nm 0.75 v FinFET Technology and compared with 14 nm Technology that is inbuilt into content addressable memory (CAM) to reduce the power consumption of CAM. The results show that the proposed design improves on a voltage basis and the complexity of the circuit is reduced by about 23% in terms of transistor count compared with the other conventional techniques. The 10 nm FinFET Hybrid Self Controlled - PreCharge Free (HSCPF) CAM design is best-suitable for low-power applications.

Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)

This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific devices. An SOI FinFET device consists of three independent gates. By connecting the various gates, multiple working modes are obtained. Compared with traditional FinFETs, the multi-enhanced operation gate fin field-effect transistor in this study combines independent gates by connecting the selection modes; thus, a possible operation can be performed to attain a FinFET with five equivalent working states in only one device. This novel function can enable the device to work with multiple specific voltages and currents by connecting the corresponding gate combinations, augmenting the integrated degrees and shifting the working modes, thereby meeting the different needs of high-speed, low-power, and other potential applications. Further, the potential applications are highlighted.

Multifunctional Ion-Sensitive Floating Gate Fin Field-Effect Transistor with Three-Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology.

A multifunctional ion-sensitive floating gate Fin field-effect transistor (ISFGFinFET) for hydrogen and sodium detection is demonstrated. The ISFGFinFET comprises a FGFET and a sensing film, both of which are used to detect and improve sensitivity. The sensitivity of the ISFGFinFET can be adjusted by modulating the coupling effect of the FG. A nanoseaweed structure is fabricated via glancing angle deposition (GLAD) technology to obtain a large sensing area to enhance the sensitivity for hydrogen ion detection. A sensitivity of 266mV per pH can be obtained using a surface area of 3.28 mm2 . In terms of sodium ion detection, a calix[4]arene sensing film to monitor sodium ions, obtaining aNa+ sensitivity of 432.7mV per pNa, is used. In addition, the ISFGFinFET demonstrates the functionality of multiple ions detection simultaneously. The sensor arrays composed of 3 × 3 pixels are demonstrated, each of which comprise of an FGFET sensor and a transistor. Furthermore, 16 × 16 arrays with a decoder and other peripheral circuits are constructed and simulated. The performance of the proposed ISFGFinFET is competitive with that of other state-of-the-art ion sensors.

TCAD Simulation Study of Single-, Double-, and Triple-Material Gate Engineered Trigate FinFETs

A detailed comparative performance analysis of the Trigate Fin Field Effect Transistor (FinFET) device with different structures such as Single-Material Gate (SMG) FinFET, Double-Material Gate (DMG) FinFET, and Triple-Material Gate (TMG) FinFET has been done. Silvaco Atlas Technology Computer-Aided Design (TCAD) tool is used to model the Trigate FinFET device structures and to characterize all the electrical parameters of the device. The simulation results confirm that TMG FinFET device structure shows better performance than SMG and DMG FinFET device structures, in terms of device electrical parameters such as surface potential, electric field, and drain current. Moreover, TMG FinFET device structure exhibits an excellent transconductance of 0.28 μA/V when compared with SMG FinFET (0.21 μA/V) and DMG FinFET (0.24 μA/V).

A Review Article on Fin Field Effect Transistors Technology

There are numerous types of transistors we have studied. Beyond them, here, we have discussed an exhaustive type of Metal Oxide Field Effect Transistor (MOSFET), that is, Fin Field Effect Transistor (FinFET). Basically, we have reviewed the most demanding and promising type of Field Effect Transistor, that allows as an exclusive easy execution of transistor applications and simulation, both in digital and analog functions. So as to improve the execution and power capability of semiconductor applications, FinFET can be implemented over bulk MOSFET and are also encouraging FETs that can perform ideally over 32 nanometers technology. And due to these, as an issue of the Short Channel Effects (SCEs) can be overcome. Through multi gate FinFET designs, bulk CMOS circuits can be implemented effectively. We will see structures, different types and their classifications and some digital circuits designed by using FinFET.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

In this paper, we present a new differential multiple-time-programmable (MTP) memory cell with a novel slot contact coupling structure in the fin field-effect transistor (FinFET) CMOS process. This MTP cell contains a pair of floating metal gates to store differential data on a single cell. Through differential read operations, the cells are less susceptible to read error caused by cell-to-cell variations. In a nano-scaled FinFET process, the gate dielectric layer becomes too thin to retain charge in the floating gates for long periods of time. Differential cell design further extends the data lifetime, even with the serious charge-loss problem, and reduces the overall intellectual property (IP) area.

A NOVEL FINFET BASED APPROACH FOR THE REALIZATION OF TERNARY GATES

The Scaling of conventional Complementary Metal Oxide Semiconductors (CMOSs) has been facing problems such as short channel effect due to hot electron effect and leakage power. Fin Field Effect Transistor (FinFET) is considered as solution to this issue. Binary system occupies large area there for the circuit complexity is increasing on a VLSI chip and thus degrading the performance of binary system. Multi valued logic MVL is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip I have designed FinFET based ternary basic gates (T-NOT, ST-NAND, ST-NOR, ST-AND and ST-OR). FinFET is classified in to two types based on gate structure: 1) Short Gate FinFET (SG-FinFET) and 2) Independent Gate FinFET (IG-FinFET). The proposed ternary logic gates are design using SG-FinFET. Simulation is performed with Tanner EDA tool. The proposed design has achieved good reduction in the circuit element count.

Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs

nanoscale n-channel double gate fin field-effect transistor (FinFET) structures and their sensitivity to gate dielectric materials with different channel materials using SiGe and 3CSiC in the channel region. In this work, the numerical tool Atlas Silvaco was used to simulate the device in three dimensions and evaluate the electrical characteristics of the device at 300K. The influence of the gate dielectrics on threshold voltage roll-off, subthreshold slope, transconductance, drain induced barrier lowering, leakage current, on-current, and on/off current ratio has been investigated. The simulation results show that high drain current and transconductance were obtained with SiGe channel material. The results also show that a higher value of gate dielectric constant can increase the drain current and improve the leakage current. Drain induced barrier lowering is reduced with the increase in gate dielectric constant. It can be noticed with different and useful results which led researchers to further manufacturing process in order to get the complete device.

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics

The high-k is needed to replace SiO 2 as the gate dielectric to reduce the gate leakage current. The impact of a high-k gate dielectric on the device short channel performance and scalability of nanoscale double gate Fin field effect transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high-k at the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer-aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified as V T =0.653V with e=23(ZrO 2 ) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47×10 -14 A. High-k improves the I on /I off ratio of transistors for future high-speed logic applications

Doping fin field-effect transistor sidewalls: Impurity dose retention in silicon due to high angle incident ion implants and the impact on device performance

The three dimensional (3D) nature of a fin field-effect transistor (FinFET) structure creates new challenges for an impurity doped region formation. For the triple gate FinFET, both top and side surfaces require high levels of dopant incorporation to minimize access resistance. In this work, we investigate the use of conventional ion implantation for the introduction of impurities in this 3D silicon structure. Specifically, we evaluate sidewall impurity dose retention at various angles of incidence. The retention of dose is determined by (i) trigonometry of the implant angle in the 3D fin system, (ii) backscattering, and (iii) material properties of the target surface. Dose retention is most sensitive to the implant angle. For a fixed implant projected range, lighter ions are more likely to be ejected from the target. Thus, heavier ions are better for dose retention. The influence of sidewall dose retention on the electrical performance of fully depleted FinFETs was investigated by means of 3D device simulation. Drive current and short channel effect control are more sensitive to dose retention on sidewalls than to dopant conformality.

High tolerance to total ionizing dose of Ω-shaped gate field-effect transistors

Ionizing radiation effects are investigated in N-channel metal-oxide-semiconductor triple-gate field-effect transistors with Ω-shaped gate fin field-effect transistor (FinFET) architecture. The total dose response is shown to be dependent on device geometry. A wide FinFET structure behaves like a single-gate fully depleted silicon-on-insulator transistor, showing a noticeable degradation induced by ionizing radiation. By contrast, an optimized narrow FinFET shows a drastically reduced influence of ionizing radiation thanks to the efficient electrostatic control of the potential in the device provided by the Ω gate. A narrow FinFET is shown to be naturally tolerant to a significant total dose exposure.