Gate Driver Circuit Research Articles

Region‐selective shift register by a single output enable signal for a multiple refresh frequency driving scheme

AbstractMany low‐power technologies have been developed for high‐performance displays. One method is to vary the refresh rate according to the input image, where frequencies are reduced over still images and slow‐moving videos. To support the variable refresh rate scheme, the programmable gate driver circuit should be integrated. This paper proposes a thin‐film transistor (TFT) shift register of which output pulse is simply controlled by an enable signal. Because the output pulse generation is directly adjusted without the previous programming period, various output pulse sequences are possible with the high flexibility. The shift register is composed by adding six TFTs and one capacitor to a conventional circuit that provides a carry pulse to a next stage. The simulation program with integrated circuit emphasis (SPICE) simulation ensures that gate pulses for any numbers of lines in any regions can be generated within one frame only by applying the enable signal at the corresponding timing, resulting in multiple refresh frequencies in a screen. In addition, it is verified that additional TFTs and capacitor contribute to only the negligible increase in power consumption by 2.1%, compared to a conventional shift register.

Efficient power conversion with four switch soft-switching boost integrated half-bridge dual-output series resonant converter

Soft switching reduces voltage and current stress during transitions, smoothing and quieting operations and reducing electromagnetic interference while also increasing efficiency and equipment lifespan. Circuit design, component selection, and switching frequency optimization affect power electronics soft switching. This paper proposes boost integrated half-bridge dual-output series resonant (BIHBDOSR) converter, a novel converter design and control method to increase series resonant converter performance by reducing storage element size, switch count, and switching losses. This methodology relies on soft-switching technologies like zero-voltage switching (ZVS) and zero-current switching (ZCS). These methods use class-D, class-E, series, parallel, and series–parallel resonant converter circuits to increase efficiency and minimize component stress. The proposed converter is ideal for constant voltage, constant power, and current-controlled loads with the output voltage being regulated by a closed-loop PI controller. The output voltages for two loads in the simulation depart from reference values. V01 changes from 14 to 20 V and V02 from 18 to 15 V at 300 ms owing to switching variances. The proposed converter utilizes gate driver circuits, resonant tank circuit, current sensor, FPGA board for closed-loop control, and current sensor for stability, ensuring converter stability. The proposed converter closed-loop control method modifies PWM signals to regulate both loads independently and ensure steady output voltage. Additionally, to validate the effectiveness of proposed converter, a 50-W driver circuit is designed, delivering two independent outputs of 20 W and 30 W. Frequency modulation (FM) and duty cycle control methods are employed to obtain the desired outputs.

A New Multiresonant Gate Driver Circuit for SiC MOSFETs

A New Multiresonant Gate Driver Circuit for SiC MOSFETs

Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels.

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control.

Dual-bootstrapping gate driver circuit design using IGZO TFTs

To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution large-size display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance–capacitance (RC) loadings and require high resolution above 8 K.

P‐73: Gate Driver Circuit to generating Multi‐Frequency Pulses using LTPO Technology

This paper proposes a gate driver circuit for the implementation of multi‐region and multi‐refresh rates. A distinctive feature of this proposed circuit is the integration of a separate control block into the existing gate driver circuit. Another is the utilization of CMOS (a combination of n‐type IGZO and p‐type LTPS) to enhance circuit reliability and reduce power consumption. This gate driver circuit can be applied to an LTPO based pixel circuit which can be using with a variable refresh rate and implemented multi‐zone and multi‐refresh rates. Through circuit simulations, the paper verifies the successful operation of multi‐refresh rates based on control signals and establishes a reduction in clock power consumption. Consequently, the proposed gate driver circuit stands as a solution for achieving high resolution and low power consumption in displays.

P‐5: 27‐inch Ultra‐Narrow‐Border LCD with a Two‐Stage Output Gate Driver Circuit

A two‐stage output gate driver circuit with a clock‐controlled inverter is proposed and investigated. High and low voltage switching of inverter diminishes the positive bias stress of amorphous silicon TFTs in the circuit. The design of one cell with two‐stage output reduces the number of blocks in the gate driver circuit by half. This circuit was successfully developed for a 27‐inch LCD product with a 1.88 mm border.

P‐4: The Technology of High‐Mobility Oxide TFT for 14inch AMOLED Display

In this paper, the technology of high‐mobility Oxide TFT, which is over 50 cm2/Vs within the whole panel, was introduced. The 14 inch AMOLED panel with the resolution of 2880*1800 and the refresh frequency of 1~144Hz was driven by oxide TFT including pixel circuits and Gate driver circuits, to decrease the cost of panel. In addition, the OLED was designed as Tandem structure to reduce the power consumption of panel.

Embedded Gate Driver Circuit With Self-Aligned InGaZnO TFTs Using Common Bootstrapped Capacitive Driving for High-Resolution WOLED Displays

Embedded Gate Driver Circuit With Self-Aligned InGaZnO TFTs Using Common Bootstrapped Capacitive Driving for High-Resolution WOLED Displays

P‐72: A Bidirectional Gate Driver Circuit with Scan Signal for Low‐Frame‐Rate LTPO AMOLED Displays

This paper presents a bidirectional gate driver circuit based on low‐temperature polycrystalline oxide thin‐film transistors for a low‐frame‐rate AMOLED display. Simulation results indicate the falling and rising times of the output waveform are all below 3.48 μs and 0.56 μs with the threshold voltage variations of TFTs, ensuring the stability of the proposed circuit. The output waveforms are also generated successfully for a frame rate of 1 Hz display panel and have no fluctuation in consecutive frames. Therefore, the proposed circuit is suitable for a low‐frame‐rate AMOLED display.

39‐1: Invited Paper: An Improved Gate Driver Using Oxide TFTs for Large OLED Displays

In this paper, we present the small area and high reliable gate driver in panels using a‐IGZO TFTs for large OLED displays. The proposed gate driver circuit has a small area structure with multiple output buffers connected to one shift register circuit. To lower the voltage stress of the pull‐down TFTs, which have the highest voltage stress among the TFTs of the gate driver, the initial voltage of those TFTs is set to low and increases according to the threshold voltage shift of TFTs during operation. It could be implemented by sensing the degradation of the TFTs using the programmable DC driving method. With these technologies, we were able to reduce the gate driver design area by 40% and improve the reliability by 30% despite reducing the circuit area. We successfully developed OLED TVs from 42 inches to 97 inches using the proposed gate driver.

A New Symmetrical Source-Based DC/AC Converter with Experimental Verification

This research paper introduces a new topology for multilevel inverters, emphasizing the reduction of harmonic distortion and the optimization of the component count. The complexity of an inverter is determined by the number of power switches, which is significantly reduced in the presented topology, as fewer switches require fewer driver circuits. In this proposed topology, a new single-phase generalized multilevel inverter is analyzed with an equal magnitude of voltage supply. A 9-level, 11-level, or 13-level symmetrical inverter with RL load is analyzed in MATLAB/Simulink 2019b and then experimentally validated using the dSPACE-1103 controller. The experimental verification of the load voltage and current with different modulation indices is also presented. The analysis of the proposed topology concludes that the total required number of components is lower than that necessary for the classical inverter topologies, as well as for some new proposed multilevel inverters that are also compared with the proposed topology in terms of gate driver circuits, power switches, and DC sources, which thereby enhances the goodness of the proposed topology. Thus, a comparison of this inverter with the other topologies validates its acceptance.

Parasitic-Based Model for Characterizing False Turn-On and Switching-Based Voltage Oscillation in Hybrid T-Type Converter

High frequency and high voltage switching converters utilizing wide bandgap semiconductors are gaining popularity thanks to their compactness and improved efficiency. However, the faster switching requirements gives rise to new challenges. A key issue is the increased oscillation of the drain–source voltage caused by the switching action of the complementary switch in the same phase or change of state of the other phase switches. The voltage stress caused by these oscillations can damage the switch. Furthermore, the high dv/dt during turning-on of one switch might result in false turn-on of the complementary switch due to the miller effect. In this paper, these issues are investigated in a T-type converter through analytical and experimental analysis. Based on the proposed analytical approach, simple and cost-wise solutions utilizing an optimum design of gate driver circuits and circuit layout modifications can be developed to cope with the aforementioned issues. A comprehensive analytical model of the converter with consideration of parasitic capacitances and inductances is developed. By performing sensitivity analysis on the model, the effect of the parasitic parameters on the drain–source voltage oscillation and gate–source voltage amplitude in case of false turn-on is studied. The validity of the model is then assessed through numerical simulations and experimental results.

Design and Implementation of Improved Gate Driver Circuit for Sensorless Permanent Magnet Synchronous Motor Control

Reliable motor control is important for electric vehicle applications. The control process requires accurate measurements of the current and rotor position information to establish correct motor control design, particularly in sensorless permanent magnet synchronous motor control systems. Practical issues regarding the motor control circuit, such as the effects of parasitic element behavior on the switching components in the insulated gate bipolar transistor-driven inverter, were discussed in this study. It analyzed the effects of parasitic elements that can cause the ringing of switching losses and affect the spike of the signal in the motor current, which must be avoided in the implementation of motor control. The gate driver circuit topology was improved to reduce this effect in motor control devices. The proposed gate driver circuit design with the ringing suppression circuit configuration achieved good performance by keeping the signal spike at less than 10% in the motor current. Furthermore, a signal spike or noise was not observed in the estimation results of rotor position when using current information as the parameter control process. Both conditions were verified by experiments on the designed motor control devices. Under these conditions, signal precision can be achieved in motor control.

Design and Transient Analysis of a 650 V/150 A GaN Power Modules With Integrated Bias Power and Gate-Drive Circuit

Design and Transient Analysis of a 650 V/150 A GaN Power Modules With Integrated Bias Power and Gate-Drive Circuit

Enhancing Pixel Charging Efficiency by Optimizing Thin-Film Transistor Dimensions in Gate Driver Circuits for Active-Matrix Liquid Crystal Displays.

Flat panel displays are electronic displays that are thin and lightweight, making them ideal for use in a wide range of applications, from televisions and computer monitors to mobile devices and digital signage. The Thin-Film Transistor (TFT) layer is responsible for controlling the amount of light that passes through each pixel and is located behind the liquid crystal layer, enabling precise image control and high-quality display. As one of the important parameters to evaluate the display performance, the faster response time provides more frames in a second, which benefits many high-end applications, such as applications for playing games and watching movies. To further improve the response time, the single-pixel charging efficiency is investigated in this paper by optimizing the TFT dimensions in gate driver circuits in active-matrix liquid crystal displays. The accurate circuit simulation model is developed to minimize the signal's fall time (Tf) by optimizing the TFT width-to-length ratio. Our results show that using a driving TFT width of 6790 μm and a reset TFT width of 640 μm resulted in a minimum Tf of 2.6572 μs, corresponding to a maximum pixel charging ratio of 90.61275%. These findings demonstrate the effectiveness of our optimization strategy in enhancing pixel charging efficiency and improving display performance.

A novel switched-capacitor based multilevel voltage boost inverter for EV interface

ABSTRACT Lithium cells are connected in parallel and series to meet the current and voltage requirements in Electric vehicles (EV). Voltage and charge equaliser techniques are employed to protect the lithium cells. These equalisation circuits introduce the loss to the circuit, and the battery pack gets disconnected if any cell is faulty. Switched-capacitor converters have become an alternative to meet the voltage requirement. This article presents a voltage boost multilevel inverter configuration for electric vehicle applications. The proposed MLI features an inherent capacitor self-balancing capability and generates an output with a nine-level range. Algorithms for capacitor voltage balancing or additional sensor circuits are not required because of intrinsic self-balancing. For generating output levels, capacitors with a voltage source with an appropriate charging/discharging pattern are used. The proposed inverter doubles the output voltage for nine levels. A comparison of components, such as the number of semiconductors, diodes, gate driver circuits, and capacitors; system parameters such as voltage gain, blocking voltage, and TSV, is presented to demonstrate the advantages of the proposed MLI over recently developed topologies.

An asymmetrical multilevel inverter with minimum voltage stress and fewer components for photovoltaic renewable-energy system

Abstract The enhanced power quality provided by multilevel inverters (MLIs) has made them more appropriate for medium- and high-power applications, including photovoltaic systems. Nevertheless, a prevalent limitation involves the necessity for numerous switches and increased voltage stress across these switches, consequently increasing the overall system cost. To address these challenges, a new 17-level asymmetrical MLI with fewer components and low voltage stress is proposed for the photovoltaic system. This innovative MLI configuration has four direct current (DC) sources and 10 switches. Based on the trinary sequence, the proposed topology uses photovoltaics with boost converters and fuzzy logic controllers as its DC sources. Mathematical equations are used to calculate crucial parameters for this proposed design, including total standing voltage per unit (TSVPU), cost function per level (CF/L), component count per level (CC/L) and voltage stress across the switches. The comparison is conducted by considering switches, DC sources, TSVPU, CF/L, gate driver circuits and CC/L with other existing MLI topologies. The analysis is carried out under various conditions, encompassing different levels of irradiance, variable loads and modulation indices. To reduce the total harmonic distortion of the suggested topology, the phase opposition disposition approach has been incorporated. The suggested framework is simulated in MATLAB®/Simulink®. The results indicate that the proposed topology achieves a well-distributed stress profile across the switches and has CC/L of 1.23, TSVPU of 5 and CF/L of 4.58 and 5.76 with weight coefficients of 0.5 and 1.5, respectively. These values are notably superior to those of existing MLI topologies. Simulation results demonstrate that the proposed topology maintains a consistent output at varying irradiance levels with FLCs and exhibits robust performance under variable loads and diverse modulation indices. Furthermore, the total harmonic distortion achieved with phase opposition disposition is 7.78%, outperforming alternative pulse width modulation techniques. In summary, it provides enhanced performance. Considering this, it is suitable for the photovoltaic system.

Solid State Pulsed Power Modulator With High Repetition Rate and Short Pulse Width for High-Speed Pulsed Lasers

This paper proposes a modular pulsed power modulator (PPM) with a short pulse width and high repetition rate for pulsed lasers. The presented PPM is based on the modular structure to use semiconductor switches with low voltage ratings since these switches have fast switching speed which is an essential requirement to generate short pulses. In addition, to make a short gate signal which is also needed to generate short pulses, a gate driver circuit which applies positive and negative voltages asymmetrically is proposed. Moreover, a heatsink structure to minimize the parasitic capacitances is presented for the high repetition rate. Furthermore, a DC-DC converter for the modular PPM is developed, which connects transformers in parallel at the primary side to achieve voltage balance without any compensation circuit. Experimental results from a 5 kV PPM with the pulse width below 20 ns and repetition rate of 1 MHz are presented to verify the proposed works.

A Comprehensive Analysis of GaN-HEMT-based Class E Resonant Inverter using Modified Resonant Gate Driver Circuit

A Comprehensive Analysis of GaN-HEMT-based Class E Resonant Inverter using Modified Resonant Gate Driver Circuit