Gate-drain Overlap Capacitance Research Articles

Ultra-Sensitive PIN-Photodiode Receiver

A monolithically integrated receiver consisting of a low-capacitance PIN photodiode and a photo-charge integrating amplifier in 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS is introduced launching a new class of ultra-sensitive optical receivers. The integrated PIN photodiode has a junction capacitance of 1.5 fF at a light-sensitive diameter of 30 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m, a responsivity of 0.39 A/W at 635 nm, and rise/fall times of 0.73/0.92 ns at a reverse bias of 20 V. The common-source amplifier integrates the photo-charges on the smallest possible integration capacitor, which is a gate-drain overlap capacitance. The data bits are reconstructed by double sampling. In such a way, the sensitivity of SPAD receivers is achieved, however without using any impact ionization. At 50 Mb/s, a sensitivity of −56.4 dBm for a bit error ratio (BER) of 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> is obtained using a wavelength of 635 nm.

A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since the degeneration inductor is not a part of a magnetic feedback loop. In addition, it allows for neutralizing the intrinsic part of the parasitic capacitance, which cannot be neglected in short-channel devices. Simulation results utilizing a standard 0.18-m CMOS process indicate a 17-29-dB improvement in the reverse-isolation performance with minimal noise figure deterioration.

Direct Measurement of Capacitance Parameters in Nanometer-Scale MOSFETs

A simple measurement method is proposed for extracting capacitances in nanometer-scale metal-oxide-semiconductor field-effect transistors (MOSFETs). The method utilizes two serially connected MOSFETs and an optional metal layer above the intermediate node between MOSFETs. Gate-drain overlap capacitance and capacitances around the intermediate node, including one related to the metal layer, can be obtained by measuring the transfer current when two MOSFETs are alternately turned on at high frequency. High sensitivity in the order of attofarad is demonstrated using silicon-on-insulator (SOI) MOSFETs with gate length of 140∼300 nm and channel width of 320 nm. The proposed method is useful not only in optimizing the high-frequency performance of the scale-down devices, but also in estimating the instability (i.e. kT/C noise) and single-electron charging effect in nanometer-scale circuits.

A 0.7V Transformer-Feedback CMOS Low-noise Amplifier for 5-GHz Wireless LAN

In this paper, we present a 0.7V low-noise amplifler(LNA) using monolithic trans- former feedback to neutralize the gate-drain overlap capacitance of a fleld-efiect transistor(FET). It is a single-ended amplifler implemented in 0.18-m CMOS technology designing for 5-GHz wire- less local-area networks (LANs). This LNA achieves a simulated power gain of 10.84dB, noise flgure(NF) of 2.4dB, and input referred 1dB compression point (P1dB) of i8dBm at 5.8GHz. Operating from a 0.7-V supply, the power consumptions for the low noise amplifler(LNA) are 4.8mW.

A 1-V, 5.5-GHz, CMOS LNA With Multiple Magnetic Feedback

A CMOS low-noise amplifier that utilizes multiple monolithic transformer magnetic feedback to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance is presented. The multiple transformer topology permits negative and positive feedback to be applied constructively, allowing for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB, and best-case third-order input intercept point of 13 dBm. The design is being implemented in a 0.13-mum CMOS technology

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless lan in 0.18-μm CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-μm CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.

A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. The dopant in the source-drain extension is assumed to segregate to the Si/SiO/sub 2/ interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail,.

Design considerations for CMOS digital circuits with improved hot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (/spl tau/) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability.

A new submicron MOSFET technology with Gate Overlap on Twin Oxide (GOTO) LDD structure

We propose a new self-aligned ITLDD process with minimum gate-drain overlap capacitance by employing a double stepped gate oxide under the overlapped gate and present our device and circuit simulation results to confirm the merits of the proposed gate-drain overlapped structures with respect to reliability and device performance by employing 2-D and 3-D device simulators.

Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /cell, namely 3 × 2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)

Quadruply Self-Aligned MOS (QSA MOS) - A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)

ZOGMOST: an improved m.o.s.t. for c.c.d. peripheral circuits

An improved formation for m.o.s. transistors fabricated with the `shadow-etch´ c.c.d. process is reported. The narrow self-aligned gaps produced by the process are used to provide an additional screen gate, which allows the gate-drain overlap capacitance to be minimised, thereby improving the frequency characteristics of linear and digital m.o.s. circuits. Depending on the gain of the stage involved, an improvement in the frequency performance of up to 5 times is expected, and practical results for the modified m.o.s.t. agree with this prediction.