GaN Growth Temperature Research Articles

The influence of GaN growth temperature on parasitic masking in SA-MOVPE using PECVD SiO2 mask

The influence of GaN growth temperature on parasitic masking in SA-MOVPE using PECVD SiO2 mask

In situ cavity length control of GaN-based vertical-cavity surface-emitting lasers with in situ reflectivity spectra measurements

We developed an in situ cavity length control of GaN-based vertical-cavity surface-emitting lasers (VCSELs) with an in situ reflectivity spectra measurement. Firstly, a temperature dependence of a center wavelength of a 40-pair AlInN/GaN DBR was investigated, resulting in a 23 nm redshift from RT to GaN growth temperature of 1100 °C. Secondly, a periodic oscillation of a reflectivity intensity during the GaN cavity growth on the DBR was clearly observed, providing precise cavity length information. Thirdly, based on both the results, we performed the in situ GaN cavity length control, showing an accuracy within a 0.5% error. We finally demonstrated the in situ cavity length control of an actual GaN-based VCSEL structure containing n-layers, a GaInN active region, and p-layers by selecting different resonance wavelengths along with the corresponding growth temperatures for the layers.

Avoiding Gallium Pollution in Close‐Coupled Showerhead Reactors, Alternative Process Routes

In contrast to the previous work which solved the problem of gallium pollution using hardware modifications, herein, the changes are examined to process conditions to reduce gallium pollution in InAlN layer. Using a model of GaN decomposition followed by gallium desorption and diffusion to the showerhead, different process conditions are used to limit either the desorption or the diffusion. Reducing the GaN growth temperature gives some improvement by reducing desorption, but affects channel mobility, likely due to increased carbon incorporation. Increasing the wafer–showerhead distance also reduces the gallium pollution, this time by a factor of around 2. Finally, using AlGaN layers instead of GaN as the channel completely removes gallium pollution, even for composition as low as 5%. It is suggested that in addition to reducing desorption due to alloying, the aluminum precursor may be acting as a getter for this gallium, and so stops it getting to the showerhead. A combination of these different approaches suggests that process conditions can significantly reduce gallium pollution in close‐coupled showerhead reactors.

Controlled SOI nanopatterning for GaN pendeo-epitaxy

Nanopatterning of GaN/AlN layers on Silicon-On-Insulator (SOI) substrates is discussed with the aim of fabricating nanopillar arrays that can be used for subsequent GaN pendeo-epitaxy. The principle of the developed epitaxy process is that GaN crystallites are grown on deformable nano-pedestals able to rotate at GaN growth temperature. The objective is to control the complete pattern profile of GaN/AlN/Si/SiO 2 pillars, both in lateral and vertical directions. Since a smaller pillar diameter should enhance the pillar rotation at growth temperature, special emphasis will be given to nanometer-scale pillars. In this context, the control of GaN/AlN vertical sidewalls is still an issue for high-resolution nanopillars. In this paper, we report on the optimization of the plasma etching processes of GaN/AlN/Si/SiO 2 stacks to reduce the slope that widens the pillar base. Overall, we achieve near perfect arrays of 100 nm diameter nanopillars obtained by combining NanoImprint Lithography (NIL) and plasma etching, with bases of 150 nm in diameter. • Nanopatterning of GaN/AlN layers on SOI substrates • Controlled GaN/AlN etched sidewalls for high-resolution nanopillars • NIL Combined with ICP to achieve near perfect arrays of 100 nm diameter nanopillars

Near-infrared electroluminescence of AlGaN capped InGaN quantum dots formed by controlled growth on photoelectrochemical etched quantum dot templates

Near-infrared electroluminescence of InGaN quantum dots (QDs) formed by controlled growth on photoelectrochemical (PEC) etched QD templates is demonstrated. The QD template consists of PEC InGaN QDs with high density and controlled sizes, an AlGaN capping layer to protect the QDs, and a GaN barrier layer to planarize the surface. Scanning transmission electron microscopy (STEM) of Stranski–Krastanov (SK) growth on the QD template shows high-In-content InGaN QDs that align vertically to the PEC QDs due to localized strain. A high-Al-content Al 0.9 Ga 0.1 N capping layer prevents the collapse of the SK QDs due to intermixing or decomposition during higher temperature GaN growth as verified by STEM. Growth of low-temperature (830°C) p-type layers is used to complete the p-n junction and further ensure QD integrity. Finally, electroluminescence shows a significant wavelength shift (800 nm to 500 nm), caused by the SK QDs’ tall height, high In content, and strong polarization-induced electric fields.

Van der Waals coherent epitaxy of GaN and InGaN/GaN multi-quantum-well via a graphene inserted layer

GaN-based films grown on sp3-bonded single-crystalline substrates can maintain the coherent growth character. However, exfoliating III-nitride films from these substrates proves difficult because of the strong sp3-type covalent bonds between the substrates and epilayers. The sp2-bonded two-dimensional (2D) materials exhibit hexagonal in-plane lattice arrangements and weakly bonded layers, so the GaN epilayer grown on 2D materials can be transferred onto foreign substrates with ease. In this paper, graphene is used as the inserted layer (IL) on freestanding GaN substrate and the van der Waals coherent epitaxy of GaN-based single-crystalline films on such graphene/GaN templates is investigated. Density functional theory computations are performed to probe the transmission of crystallographic information of wurtzite GaN through the graphene IL. The appropriate layer numbers of graphene IL and GaN growth temperature are optimized to demonstrate the coherent epitaxy character. Both theoretical and experimental results support that the coherent epitaxy of GaN can only be achieved by using a monolayer graphene IL, and the crystalline quality of optimized GaN film can reach the same level of that grown directly on GaN freestanding substrates.

GaN buffer growth temperature and efficiency of InGaN/GaN quantum wells: The critical role of nitrogen vacancies at the GaN surface

An indium-containing layer positioned underneath the InGaN/GaN quantum well (QW) active region is commonly used in high efficiency blue light-emitting diodes. Recent studies proposed that the role of this underlayer is to trap surface defects (SDs), which, otherwise, generate non-radiative recombination centers in the QWs. However, the origin and the nature of these defects remain unknown. Our previous study revealed that high-temperature growth of GaN promotes SD creation. In this work, we investigate the impact of the GaN-buffer growth temperature on the InGaN/GaN QW efficiency. We show that the 300 K photoluminescence decay time of a single QW deposited on 1-μm-thick GaN buffer dramatically decreases from few ns to less than 100 ps when the GaN buffer growth temperature is increased from 870 °C to 1045 °C. This internal quantum efficiency collapse is ascribed to the generation of SDs in the GaN buffer. A theoretical study of temperature-dependent defect formation energy in GaN suggests that these SDs are most likely nitrogen vacancies. Finally, we investigate the formation dynamics of SDs and show that they are mainly generated at the early stage of the GaN growth, i.e., within 50 nm, and then reach a steady state concentration mainly fixed by the GaN growth temperature.

Role of V-defect density on the performance of III-nitride green LEDs on sapphire substrates

In this study, we experimentally investigated the role of V-defect density on the performance of green III-nitride LEDs grown on sapphire substrates by metalorganic chemical vapor deposition. We systematically varied the threading dislocation (TD) density from 4 × 108 to 1 × 109 cm−2 by changing the V/III ratio during initial high temperature GaN growth. A 30-period InGaN/GaN superlattice promoted V-defect formation and growth at TDs, where the density of V-defects was correlated to the TD density. By interrupting the LED growth and examining the surface of the active region, we quantified the average size and density of V-defects. In a series of LEDs, we measured a systematic decrease in forward voltage (VF) with V-defect density. At a V-defect density of 5.0 × 108 cm−2 and TD density of 1 × 109 cm−2, green LED devices were demonstrated with λ = 523 nm and VF = 2.94 V at 20 A cm−2. These results highlight the potential of using V-defect engineering to achieve low VF long wavelength LEDs on sapphire substrates, where opening of remaining threading dislocations into V-defects presents an opportunity for further VF reduction.

Color‐Tunable 3D InGaN/GaN Multi‐Quantum‐Well Light‐Emitting‐Diode Based on Microfacet Emission and Programmable Driving Power Supply

AbstractColor‐tunable InGaN/GaN multi‐quantum‐well (MQW) light‐emitting diodes (LEDs) are reported based on GaN microfacet structure directly grown on c‐plane patterned sapphire substrate by metal organic vapor phase epitaxy (MOVPE) through promoting 3D growth. By adjusting GaN growth temperature and pattern arrangement, a GaN microfacet with almost pure {101} semipolar facets is obtained. The multifacetted InGaN/GaN MQW LED chip evolves three distinct emission peaks around 630, 530, and 450 nm in electroluminescence (EL) as injection current increases from 1 to 100 mA. The EL behavior originates from locally different facets of the complex 3D structure: MQWs grown on c‐planes and semipolar facets, respectively, which is confirmed by cathodoluminescence characterization in a scanning transmission electron microscope (STEM‐CL). Considering the dependence of emission wavelength and intensity on injection currents, a programmable power supply is designed to drive the LED. The specific color of the LED is tuned by time‐shared driving of the currents based on three channels with controllable magnitudes and duty cycle from the power supply, covering red, yellow, green, cyan, blue, and purple. Furthermore, white LEDs with high color rendering index (CRI) up to 96.1 and correlated color temperature (CCT) between 4000 and 10 000 K are achieved.

Molecular beam epitaxial growth and optical characterization of AlGaN nanowires with reduced substrate temperature

The requirement of high growth temperature for high-quality epitaxial AlGaN, which is typically around 100 °C higher than the growth temperature of GaN, is unfavorable for p-type dopant (Mg) incorporation, representing a grand challenge for AlGaN deep ultraviolet (UV) light-emitting devices. In this context, we show high-quality AlGaN nanowires emitting in the deep UV band grown at merely the growth temperature of GaN nanowires by molecular beam epitaxy. This is enabled by the discovery of a narrow GaN nanowire template growth window. We have further compared the room-temperature internal quantum efficiency of the samples emitting around 255 nm grown in the low-temperature regime and high-temperature regime. It is found that the sample grown in the low-temperature regime can possess optical quality close to the sample grown in the high-temperature regime. This study, therefore, suggests that even with a low growth temperature, using nanowire structures can still lead to AlGaN alloys with a relatively high optical quality, and the use of low substrate temperature could be beneficial for p-type doping.

Microstructural Evolution of MOVPE Grown GaN by the Carrier Gas

We report the effect of total carrier gas flow of GaN during both GaN nucleation layer and high temperature GaN growth steps on structural, optical, electrical and morphological properties. The formation of dislocations in GaN layer and their effects were investigated in detail as a function of carrier gas flow. It has been found that the more carrier gas requires longer recovery time for transition from 3D (3 dimensional) to 2D growth and results in smaller edge-type dislocation density. The images obtained from the AFM measurements have shown terraces widths varying between 60–150 nm depending on the hydrogen flow rate.

Features of the Initial Stage of GaN Growth on Si(111) Substrates by Nitrogen-Plasma-Assisted Molecular-Beam Epitaxy

The results of investigations of the effect of the initial conditions (nitridation of the Si(111) substrate, the GaN growth temperature, and the stoichiometry of GaN growth) on the growth kinetics and the GaN/Si(111)-layer polarity under nitrogen-plasma-assisted molecular-beam epitaxy are presented. It is experimentally established that the optimal initial condition for GaN epitaxy on Si(111) substrates is high-temperature nitridation of the Si(111) substrate carried out immediately before GaN growth. It is shown that it is possible to control the polarity of GaN by means of appropriate choice of the growth under conditions with N or Ga enrichment at the initial stage of GaN/Si(111) epitaxy.

(Invited) Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process

Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

(Invited) Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process

Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, InGaP LED, GaAs HBT, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN LED or HEMT on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

Особенности начальных стадий роста GaN на подложках Si(111) при молекулярно-пучковой эпитаксии с плазменной активацией азота

AbstractThe results of investigations of the effect of the initial conditions (nitridation of the Si(111) substrate, the GaN growth temperature, and the stoichiometry of GaN growth) on the growth kinetics and the GaN/Si(111)-layer polarity under nitrogen-plasma-assisted molecular-beam epitaxy are presented. It is experimentally established that the optimal initial condition for GaN epitaxy on Si(111) substrates is high-temperature nitridation of the Si(111) substrate carried out immediately before GaN growth. It is shown that it is possible to control the polarity of GaN by means of appropriate choice of the growth under conditions with N or Ga enrichment at the initial stage of GaN/Si(111) epitaxy.

Monolithic Integration of Si-CMOS and III-V-on-Si Through Direct Wafer Bonding Process

Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

Site-controlled GaN nanocolumns with InGaN insertions grown by MBE

The site-controlled plasma-assisted molecular beam epitaxy (PA MBE) has been developed to fabricate the regular array of GaN nanocolumns (NCs) with InGaN insertions on micro-cone patterned sapphire substrates (μ-CPSSs). Two-stage growth of GaN NCs, including a nucleation layer grown at metal-rich conditions and high temperature GaN growth in strong N-rich condition, has been developed to achieve the selective growth of the NCs. Microcathodoluminescence measurements have demonstrated pronounced emission from the InGaN insertions in 450-600 nm spectral range. The optically isolated NCs can be used as effective nano-emitters operating in the visible range.

Thermal etching rate of GaN during MOCVD growth interruption in hydrogen and ammonia ambient determined by AlGaN/GaN superlattice structures

Thermal etching effect of GaN during growth interruption in the metalorganic chemical vapor deposition reactor was investigated in this paper. The thermal etching rate was determined by growing a series of AlGaN/GaN superlattice structures with fixed GaN growth temperature at 735°C and various AlGaN growth temperature changing from 900°C to 1007°C. It was observed that the GaN layer was etched off during the growth interruption when the growth temperature ramped up to AlGaN growth temperature. The etching thickness was determined by high resolution X-ray diffractometer and the etching rate was deduced accordingly. An activation energy of 2.53eV was obtained for the thermal etching process.

(Invited) Gallium Nitride on Silicon

Beginning with the first GaN-based high electron mobility transistor (HEMT) fabricated in 1993, the most noteworthy advantage of III-nitride materials over other wide bandgap semiconductors is the implementation of heterostructures. The commercially employed AlGaN/GaN heterostructure exhibits a sheet charge as a result of the large spontaneous and piezoelectric polarization-induced field and large conduction band offset. This built-in field induces a two-dimensional electron gas (2DEG) that is linearly proportional to the Al-mole fraction. A 2DEG density greater than 1013 cm-2 represents a 5–10x gain above typical GaAs or InP pHEMTs. The associated mobility at this high current density is 1,300–2,000 cm2/Vs. Remarkable progress has been made in high-performance GaN HEMTs grown on a variety of substrates. In fact, the commercial success of the GaN HEMT is directly attributable to the ability to deposit high-quality thin films on non-GaN substrates. There are principally three substrates that have been utilized with heteroepitaxial GaN-based devices: sapphire, SiC, and silicon. While several other materials have been used as substrates for depositing III-Nitride thin films, many with good crystalline quality, the vast majority of research and development efforts have focused on the aforementioned substrate materials. GaN HEMT device performance design poses multiple, often divergent, challenges to the optimal substrate material selection. In other words, comparing the various substrate options, there is not one perfect material choice. The unique requirements of each application dictates the decision regarding the best substrate. When it comes to substrate size and cost, undoubtedly, silicon is best. Therefore, GaN-on-Si heteroepitaxy has leveraged the development and refinement of this near-perfect crystalline semiconductor material. Furthermore, over many decades, the silicon industry has refined a wide range of substrate electrical resistivities, both n- and p-type. While the high-quality, low-cost, and large-diameter of Si substrates are well understood, other inherent advantages of GaN-on-Si include the ability to leverage established Si processes for wafer grinding and polishing, via-hole formation, and AuSi eutectic die attach. GaN-on-Si HEMTs have employed substrates with the resistivity tailored to the application; particularly p-type for power switching and intrinsic (float-zone, highly resistive) for RF power amplifiers. Historically, the lack of early adoption of GaN-on-Si was attributable to the technical challenges presented by the ~17% lattice mismatch and ~56% thermal expansion coefficient mismatch between GaN and Si (111). To address these, development efforts led to stress-accommodating nucleation and transition layer schemes, allowing growth of crack-free and low warp (Al,Ga,In)N layers on high quality, low-cost, large-diameter Si substrates. Si has a reasonable thermal conductivity that is similar to bulk crystalline GaN, but inferior to competing substrates; principally SiC-based. This is a key design consideration for exploitation of the exceptional power density offered by GaN HEMTs. The inferior Si substrate thermal conductivity can limit device scaling, which is a factor in applications where the junction temperature rise is limited. These mismatches have been researched extensively and several techniques to overcome their impact on epitaxial crystal quality have been developed, and will be discussed. Silicon’s “thermal stability,” meaning its relative inertness at typical GaN growth temperatures, greater than 1000 °C, is also inferior to SiC and sapphire. This can result in auto-doping of the Si substrate during nucleation of the GaN epitaxy. In particular, the Al and Ga, whether introduced in the growth chamber intentionally or unintentionally, can diffuse into the silicon from the gas phase creating a p-doped layer at the surface of the substrate. While considerable work has been done to mitigate the auto-doping effect for RF amplifier applications at higher frequencies (above ~ 6GHz) the capacitive coupling of this conductive layer can limit the dc-to-RF conversion efficiency of the device. These efforts will be reviewed and compared. Finally, the generally applied principle for fabricating GaN-on-Si devices has been to utilize traditional III-V processes. However, recent efforts have also incorporated more “Si-like” processing techniques to leverage existing silicon fab excess capacity. The heteroepitaxial growth and processing techniques developed for GaN-on-Si HFET fabrication will be reviewed, and future directions will be offered.

Vertically Oriented Growth of GaN Nanorods on Si Using Graphene as an Atomically Thin Buffer Layer.

The monolithic integration of wurtzite GaN on Si via metal-organic vapor phase epitaxy is strongly hampered by lattice and thermal mismatch as well as meltback etching. This study presents single-layer graphene as an atomically thin buffer layer for c-axis-oriented growth of vertically aligned GaN nanorods mediated by nanometer-sized AlGaN nucleation islands. Nanostructures of similar morphology are demonstrated on graphene-covered Si(111) as well as Si(100). High crystal and optical quality of the nanorods are evidenced through scanning transmission electron microscopy, micro-Raman, and cathodoluminescence measurements supported by finite-difference time-domain simulations. Current-voltage characteristics revealed high vertical conduction of the as-grown GaN nanorods through the Si substrates. These findings are substantial to advance the integration of GaN-based devices on any substrates of choice that sustains the GaN growth temperatures, thereby permitting novel designs of GaN-based heterojunction device concepts.