GaN-based Field Effect Transistors Research Articles

Improvement of reverse conduction characteristic and single event effect for a novel vertical GaN field effect transistor with an integrated MOS-channel diode

A vertical GaN-based field-effect transistor with an integrated MOS-channel diode (MCD) is used to improve the reverse conduction characteristic and transient single-event effect (SEE). The device features an MCD acting as a free-wheel diode formed between trench source metal on the source dielectric and a P-type blocking layer (PBL), wherein MIS structure is formed by trench source, source dielectric and N-drift. At the reverse conduction (VSD > 0 V, VGS ≤ 0 V), because the channel between the PBL and the MIS structure is opened, the MCD turns on to realize a low reverse turn-on voltage (VRT) and the VRT is independent of VGS. At the forward conduction (VDS > 0, VGS > Vth), the MCD is pinched-off without influencing the on-state characteristic of the MCD-FET. Moreover, owing to the modulation effect of the PBL on electric-field distribution, both the impact ionization rate and transient SEE peak current (Ipeak) is reduced. Consequently, a low VRT = 0.67 V, low Ipeak = 10.11 mA and high BV = 1573 V are achieved. The VRT and Ipeak are decreased by 46.4 % and 64.9 %, respectively, compared with those of the conventional current aperture vertical electron transistor (CAVET).

Nonequilibrium electron-phonon coupling across the interfaces between Al nanofilm and GaN.

The metal Al is commonly attached to external circuits as the source and drain in GaN-based field effect transistors, so profound comprehension of the energy transfer between electrons and phonons in Al/GaN is crucial for nanofabrication and thermal management of electronic devices. Time-domain thermoreflectance (TDTR) is an effective technique for measuring the strength of non-equilibrium electron-phonon (e-ph) coupling. The two-temperature model (TTM) is widely employed in conjunction with TDTR methods to determine e-ph coupling factors. However, TTM is a gray method and cannot take into account interactions between electrons and different phonon modes. Therefore, in this work, we use the TDTR technique to analyze the non-equilibrium transport properties of pure Al and the thickness dependence of the e-ph coupling with Al nanofilms, and the coupling strengths of high-energy electrons excited by femtosecond lasers with different modes of phonons are obtained in conjunction with MTM. The results show that the e-ph coupling coefficients of Al nanofilms on GaN substrates are larger than those of pure Al. In conjunction with the TTM, we determined the coupling strength between high-energy electrons excited by femtosecond laser pulses and various phonon modes. Compared to the transverse acoustic branch-1 (TA1) and transverse acoustic branch-2 (TA2) modes, the longitudinal acoustic (LA) phonon mode of Al exhibits a higher e-ph coupling factor. This suggests that the LA mode predominates in the electron relaxation process after ultrafast femtosecond laser excitation. This study provides experimental and theoretical guidance for laser processing and electronic device design.

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

The effects of gas exposure on the graphene/AlGaN/GaN heterostructure under UV irradiation

This work demonstrates a graphene/AlGaN/GaN sensing device with two-dimensional electron gas (2DEG) toward nitrogen dioxide (NO2), tetrahydrofuran, and acetone detection under UV light irradiation. We propose combining measurements of the DC characteristics with a fluctuation-enhanced sensing method to provide insight into the gas detection mechanisms in the synergistic structure of highly stable GaN and gas-sensitive graphene. Both DC and low-frequency noise studies reveal the impact of UV irradiation (275 nm) on the GaN-based field-effect transistor (FET). Gas detection improves under UV light with higher differentiability between selected concentrations of inorganic (NO2) gas and the possibility of discrimination between weakly adsorbing organic species (tetrahydrofuran and acetone). Time-domain experiments confirm the stability and reversibility of sensor (short-time and long-time) responses and reduced time drift after employing UV light. Features observed in the 1/f noise spectra may indicate the high impact of the irradiation on the trapping states in the GaN-based heterostructure, which further modulates the fluctuations of the channel carriers in our device. Our findings broaden the view on AlGaN/GaN heterostructures modulated with a graphene gate for gas sensing purposes, including strongly binding inorganic gas and weakly adsorbing organic species.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride (GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules. Recently emerging GaN-based p-channel field-effect transistors (FETs) and monolithic integration techniques enable the implementation of GaN-based complementary logic (CL) circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functionality. In this article, holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems, based on the material limit of GaN and state-of-the-art experimental results. It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform could be as short as sub-nanosecond, which sufficiently satisfies the requirement of power conversion systems typically with operating frequencies less than 10 MHz. With the currently adopted n-FET-based logic gates (e.g., directly coupled FET logic) replaced by CL gates, the power consumption of peripheral logic circuits could be substantially suppressed by more than 103 times, mainly due to the elimination of the pronounced static power loss. Consequently, the energy efficiency of the entire system could be substantially improved.

GaN-based complementary inverter logic gate using InGaN/GaN superlattice capped enhancement-mode field-effect-transistors

GaN-based high electron mobility transistors (HEMTs) have received much attention due to their potential usage in radio-frequency and high power applications. However, the development of logic gates has remained mostly elusive due to the still challenging reliable operation of the field-effect enhancement-mode n-transistor and nascent stage for the p-transistor. The n-transistor behavior is mainly achieved by combining the aggressive thinning down of the barrier layer, using charged oxides, and p-doping the cap layer. The p-transistor generally requires a heavily doped p-GaN layer. The realization of both transistors on the same substrate remains challenging due to the conflicting requirements for n- and p-transistors. Here, we propose a GaN-based field-effect complementary transistor device using a p-doped InGaN/GaN superlattice (SL) structure on top of the barrier layer of the HEMT heterostructure. The SL structure changes the electrostatics of the heterostructure by the formation of a two-dimensional hole gas region. An undoped SL structure is shown to be enough to lift the conduction band-edge above the Fermi level to convert the n-transistor from depletion-mode (D-mode) to enhancement-mode (E-mode). The lifting of the bands, in turn, creates a natural quantum-well for the holes in the p-transistor. An additional p-doping of the SL moves the threshold voltage of the E-mode n-transistor further into a positive direction and increases the hole density in the quantum-well E-mode p-transistor. The SL structure, which can be grown by a standard epitaxial process, facilitates the realizations of both the n- and p-transistors. The characteristics of individual devices are further analyzed. A digital inverter gate is simulated, and critical static and dynamic performance parameters are reported. The propagation delay indicates that logic operations can be done at a very high speed compared to those offered by other conventional semiconductors.

Effects of SiON/III-nitride interface properties on device performances of GaN-based power field-effect transistors

In this work, we performed an investigation on the electrical characteristics of the interfaces of SiON/AlGaN and SiON/GaN by fabricating a partially gate-recessed metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) and a fully gate-recessed metal-insulator-semiconductor field-effect transistor (MIS-FET). The fabricated MIS-HEMT exhibits a smaller static on-resistance (R on) of 12.7 Ω · mm, while the MIS-FET achieves the normally-off operation. As a result of over-etching in the gate trench, a higher trap state density of 2 × 1013 cm−2eV−1 at the SiON/GaN interface in comparison to SiON/AlGaN interface (8 × 1012 cm−2eV−1), leading to a more obvious degradation of subthreshold swing, was extracted after performing the high temperature I DS−V GS tests. In addition, compared with the MIS-FET, the traps distributed at the SiON/AlGaN interface are found to be located at a deeper energy level, which make the device more stress sensitive and can cause a greater threshold voltage (V th) shift in the drain-bias stress measurement. The drain-bias stress at off-state increases the ionized trap density and makes the ionized traps unrecoverable within 1000 s in the MIS-HEMT. This work reveals the different properties of traps states at the SiON/AlGaN and SiON/GaN interfaces, and their effects on the device reliability.

GaN Vertical-Channel Junction Field-Effect Transistors With Regrown p-GaN by MOCVD

We report an experimental demonstration of GaN-based vertical-channel junction field-effect transistors (VC-JFETs). A p-GaN regrowth by metalorganic chemical vapor deposition (MOCVD) and a subsequent self-planarization process were developed to fabricate the GaN VC-JFETs. Fin-like channel regions were patterned by electron beam lithography (EBL) and aligned to ${m}$ -plane or ${a}$ -plane. The electrical properties of lateral and vertical p-n junctions were characterized to verify the effectiveness of the p-GaN regrowth. Both VC-JFETs with ${m}$ -plane and ${a}$ -plane channels show decent gate modulation. We further discussed important factors that may affect the device performance including interfacial impurities and nonuniform acceptor distribution. This work highlights the successful demonstration of GaN VC-JFETs and lateral p-n junctions by an etch-then-regrow process, providing valuable information and reference for the further development of GaN power electronics.

Design of Ion-Implanted Junction Termination Extension for Vertical GaN Pin Rectifiers

In recent years, GaN bipolar switches have attracted much research interests for the implementation of high-power and high-voltage applications that laterally-scaled GaN-based power field-effect transistors were not optimally implemented. In the context of vertical power device design, a proper electric field engineering would be of crucial importance to exploit the device performance that could potentially reach the theoretical power switching limit for a given material system. In this report, we studied the effectiveness of the floating guard ring design of a vertical GaN p-i-n (PIN) rectifiers for kV-range applications using a planar device fabrication that involves the use of ion-implantation as a mean of device isolation and the formation of floating guard rings. We found the gap between floating guard ring has major impact on the electric field distribution in vertical PIN rectifiers. As a result, 1 kV of blocking voltage was achieved by 6 floating guard ring design using nitrogen-ion implanted isolation.

Steep Subthreshold Swing in GaN Negative Capacitance Field-Effect Transistors

Due to the Boltzmann distribution of carriers, the subthreshold swing (SS) of traditional metal-oxide- semiconductor field-effect transistors (MOSFETs) is above 60 mV/dec at room temperature. In this article, GaN-based negative capacitance field-effect transistors (NCFETs) were fabricated by introducing HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /P(VDF-TrFE) stack as the gate dielectric layer. With the voltage amplification effect of the ferroelectric, the GaN NCFETs demonstrate the ultralow SS value of 36.3 mV/dec at room temperature, which also advances the MOSFETs in terms of saturation current (633.4 μA/μm) and ON - OFF ratio (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ). Therefore, this article demonstrates the feasibility of NCFETs for breaking the Boltzmann limit in III-V semiconductors-based transistors and opens up an avenue for switching electronic devices for portable applications.

Structural stability and band alignment in the c-plane ZnO/GaN heterostructure

The structural stability and electronic properties of ZnO on c-plane GaN substrates with and without a Ga-adlayer or Ga-bilayer are studied by first-principles calculations. The ZnO/GaN heterostructures are determined by a layer-by-layer mode from the initial adsorption of the alternative Zn and oxygen atomic layers of the first ZnO unit cell on c-plane GaN surfaces. The Ga-adlayer occupies the T4 sites of GaN (0001) substrates and improves the ordered structure of the grown ZnO. The atomic and the electronic structures are systematically analyzed for the optimized ZnO/GaN heterojunction. The perfect Zn-terminated ZnO/GaN (000) heterostructure has a band gap 2.57 eV and small band offset values, which is a potential candidate for GaN-based semiconductor heterojunction field-effect transistors devices. The Ga-adlayer induces in-gap states and causes a decrease of the band offsets for the Zn-terminated ZnO/GaN (000) heterojunction.

(Invited) GaN-Based Multiple 2DEG Channel BRIDGE (Buried Dual Gate) HEMT Technology for High Power and Linearity

We report on a GaN-based field effect transistor with laterally-gated multiple 2DEG channels, called BRIDGE (buried dual gate) HEMT. Unique operation principle of the transistor enables unprecedented device characteristics suitable for efficient and linear millimeter-wave power amplifier applications. The lateral gate simultaneously modulate multiple 2DEG channels formed in an Al(Ga)N/GaN hetero-structure. A higher electron saturation velocity measured for a lower 2DEG density suggests that the multiple 2DEG channel structure is ideal for obtaining a high current density, and simultaneously enhancing high frequency performance of the transistor. The BRIDGE HEMTs built on a 16-channel HEMT epitaxial structure with a net 2DEG density of 3.3×1013 cm-2 exhibited a record high knee current density of 3.7 A/mm. The absence of the top contact gate results in negligible current collapse by eliminating a high electric field region at the drain end of the gate – another key feature of the BRIDGE HEMT.

Demonstration of a GaN-Based Vertical-Channel JFET Fabricated by Selective-Area Regrowth

One of the key challenges for vertical GaN power devices is their complex fabrication process. We present the first experimental realization of a GaN-based vertical-channel junction field-effect transistor. A selective-area regrowth process was developed to epitaxially form the lateral p-n junction used for current control in the channel. First devices fabricated show an ${R}_{\mathrm{ON}}=\textsf {2.36}\,\,\text {m}\Omega \text {cm}^{{2}}$ and demonstrate basic current modulation. We discuss the device characteristics and limitations. Based on a TCAD model fitted to the experimental data, we explore the design rules for future device implementation.

Proposal and Demonstration of GaN-Based Normally-Off Vertical Field-Effect Transistor with a Design of Back Current Block Layer

Vertical field-effect transistor (VFET) structure has the advantage in improving both the breakdown voltage (BV) and on-resistance (RON) of semiconductor power devices when compared with the lateral devices. GaN-based normally-off VFET device is designed and demonstrated in this work and an additional back current block layer (B-CBL) is proposed and employed to further improve the device performances. By introducing the B-CBL design, the electric field distribution along the gate aperture is more uniform which leads to an obvious increase (~30%) of BV in the proposed device while the RON is kept nearly constant. Therefore, the figure of merit (FOM) value of the proposed VFET is improved apparently in comparison with that of the conventional GaN-based VFET devices.

Investigation into the carrier distribution and energy-band profile in AlGaN/GaN heterostructures with a graded AlGaN buffer

In GaN-based high-electron mobility transistors, although excellent electron confinement has been demonstrated using a graded AlGaN buffer with linearly decreasing Al-content along [0001] direction, guidelines for graded buffer design are still lacking. To obtain overall pictures of the carrier distribution and energy-band profile in AlGaN/GaN/graded AlGaN buffer heterostructures, the influences of the related physical parameters of the buffer are studied by one-dimensional self-consistent simulation. The results show that the negative polarization charge over the buffer can induce free holes in the depths of the buffer, resulting in the coexistence of electrons and holes. By adjusting the related physical parameters of the buffer, it is even possible to form two-dimensional holes gas (2DHG) at the channel/graded buffer interface. The cause of the coexistence of electrons and holes and the formation condition of 2DHG are analyzed. In addition, in the course of the variation of the related physical parameters, the characteristics of the two-dimensional electron gas density are also exhibited. This study can provide a reference for graded AlGaN buffer design in GaN-based field-effect transistors.

GaN-Based Field-Effect Transistors With Laterally Gated Two-Dimensional Electron Gas

In this letter, we report on GaN-based field-effect transistors with laterally gated two-dimensional electron gas (2DEG). The drain current of the transistor is controlled solely by modulating the width of the 2DEG between buried gates. The lateral Schottky gate contact to the GaN channel layer enhances electron confinement by raising electrostatic potential below the 2DEG, improving isolation between the source and drain. Complete elimination of a top-contact gate reduces the density of trapped electrons near the surface and alleviates capacitive coupling between the trapped electrons and the 2DEG. Owing to the unique device structure and operation principle, the 150-nm-gate transistors with a channel width of 250 nm demonstrated: extremely small output conductance, drain-induced barrier lowering, knee voltage, and knee current collapse, greatly reduced ${g}_{m}$ derivatives near threshold, and nearly constant RF gain along the resistive load line. Furthermore, a preliminary accelerated life test indicated enhanced device reliability due to an absence of the inverse piezoelectric effect. The proposed transistors hold great promise for realizing reliable and efficient power amplifiers with improved transistor linearity.

Hexagonal to monoclinic phase transformation in Eu2O3 thin films grown on GaN (0001)

The high-pressure hexagonal phase of Eu2O3 has been grown epitaxially on C-plane GaN (0001) by molecular beam epitaxy. A structural phase transition from the hexagonal to the monoclinic phase is observed with increasing film thickness by ex-situ X-ray diffraction. The critical thickness for the structural transition is between 2 and 6 nm. The observed epitaxial relationships between the substrate and the film are GaN (0001) ǁ Eu2O3 (0001), GaN ⟨112¯0⟩ ǁ Eu2O3 ⟨112¯0⟩ for the hexagonal phase, and GaN (0001) ǁ Eu2O3 (201¯), GaN ⟨112¯0⟩ ǁ Eu2O3 [020] with six rotational domains for the monoclinic phase. The (0.8 ± 0.2) eV conduction band offset and bulk dielectric constant of ∼14 makes Eu2O3 a possible gate dielectric for a GaN-based field effect transistor.

GaN-Based Junctionless Field-Effect Transistor with Hetero-Gate Dielectric for Enhancement of Direct Current and Radio Frequency Performance

GaN-Based Junctionless Field-Effect Transistor with Hetero-Gate Dielectric for Enhancement of Direct Current and Radio Frequency Performance

(Invited) A Discussion on the Latest Performance of Gan–Based Vertical Devices and the Paths Forward

Recent progress in vertical Gallium Nitride (GaN)-based power electronic devices has been compelling. Thanks to dedicated programs like the ARPA-E SWITCHES, which led to the understanding of the challenges, while enabling several variants of vertical devices to be studied and compared. An overview of different flavors of vertical devices and their latest performance will be presented. Under the SWITCHES program, in collaboration with UCSB, NRL and Transphorm, we pursued two novel and practical approaches that had the common theme of markedly reducing the required device chip size compared to commercially available lateral GaN-on-Si HEMTs. CAVET [1,2] was investigated where the gated region was implemented with p-type layer on an n-channel. The study allowed us to understand the limitation of an ion-implanted current blocking layer in a 3-terminal vertical FET configuration, eliminating restrictions imposed by poor gate dielectric. In order to achieve a ‘true’ vertical transistor, OGFET, a variant of MOSFET, was developed [3,4] where, unlike the CAVET, the gating was also performed on electrons traveling perpendicular to the surface. From a CAVET, we have successfully achieved dispersion-less switching under 500ns pulses (under Pulsed I-V measurements), and over 1100V blocking in OGFET where scaling of the devices to 1A was recently achieved. While the successes of these devices speak volumes about the future possibilities and roadmap, the technical challenges are substantial. The overarching issue is related to the realization of a well-behaved buried p-n junction, which forms the basic building block of most vertical transistors for power electronics. Fundamentally, all of them require Mg based doping, and therefore the issues related to Mg activation in GaN impact everyone. Mg is a deep acceptor in GaN offering less than 1% activation under room temperature. In addition to the RT ionization related challenges, buried p-GaN activation (this strictly means the activation from hydrogen that tend to form Mg-H complexes passivating the acceptors) is a proven concern. In short, the difficulties in achieving well-behaved buried p-GaN have stunted the possibility of realizing well-behaved (buried) p-n junctions critical to vertical devices. In a MOSFET the p-layer is grown during the initial growth of the structure. This guarantees a well-behaved p-type GaN. Similar to the reports by various groups like Toyoda Gosei and HRL[5,6], Gupta et al. (UCSB) [4] showed via OGEFT that trenched vertical devices deliver promisingly high voltage results with a path towards low On-resistance (Ron). Recently Ji et al (UC Davis) [7] successfully delivered scaled devices capable of offering 1A current with 144 unit cells in parallel. Ron <4.4mΩ.cm2 was achieved in these devices, which can be lowered further with improvement in the channel mobility. Normally-off in design, the MOSFETs definitely are attractive for the economic use of the chip area and their compatibility with presently used gate drivers A parameter to address with future research is the channel mobility to deliver lower Ron. While the typical behavior of a good gate oxide (like low trapping and small threshold voltage (Vth) shifts) also apply for these devices, the gates being designed on the sidewalls (being a or m-plane) ensure higher threshold voltages compared to c-plane HEMTs or CAVETs. This definitely alleviates the well-known tradeoff of Ron and threshold Vth to a vast degree. This talk will go over all the major achievements made over the last three years, and lay out the challenges for achieving 1.2KV switches with Ron<3mΩ.cm2 S. Chowdhury, et al., “CAVET on bulk GaN substrates achieved with MBE-regrown AlGaN/GaN layers to suppress dispersion,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 41-43, Jan. 2012.S. Mandal, et al., “All-GaN Mg ion-implanted current blocking layer CAVET demonstrating over 500V blocking voltage,” in International Workshop on Nitride Semiconductors (IWN), Orlando, USA, 2016.W. Li, et al., “Design and fabrication of a 1.2kV GaN-based MOS vertical transistor for single chip normally off operation,” Phys. Status Solidi A., vol. 213, no. 10, pp.2714-2720, Oct. 201C. Gupta, et al., “OG-FET: An in- situ Oxide, GaN interlayer based vertical trench MOSFET,” IEEE Trans. Electron Devices., vol. 37 , no. 12, pp. 1601-1604, Oct. 2016.H. Otake, et al., "Vertical GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates", Applied Physics Express, vol. 1, no. 1, p. 011105, 2008.R. Li, et al., "600 V/ 1.7 Ω Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor", IEEE Electron Device Letters, vol. 37, no. 11, pp. 1466-1469, 2016.D.Ji et.al, "Scaling GaN OGFET with MOCVD regrown n-GaN insert layer as the channel", 75th Annual Device Research Conference (DRC), Jun. 2017.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.