GaAs Metal-oxide-semiconductor Capacitors Research Articles

GaAs Metal–Oxide–Semiconductor Capacitor With Nd-Based High-k Oxynitrides as Gate Dielectric and Passivation Layer

GaAs metal–oxide–semiconductor capacitors with NdTaON as gate dielectric and NdAlON, NdON or AlON as interfacial passivation layer (IPL) are fabricated, and their interfacial and electrical properties are compared with their counterpart without IPL. Experimental results show that owing to the suppressed hygroscopicity of NdON by Al incorporation, best improvements in electrical properties and reliability are achieved for the sample with NdAlON IPL (low interface-state density ( $8 \times 10^{11}$ cm−2/eV), small flatband voltage (0.72 V), negligible hysteresis (43 mV), small frequency dispersion, and low gate leakage current density ( $2.56 \times 10^{-6}$ A/cm2 at Vfb + 1 V). These should be attributed to suppressed growth of unstable Ga and As oxides on the GaAs surface and reduced in-diffusion of elements from the gate dielectric to the GaAs surface by the NdAlON IPL during gate-dielectric annealing.

Improved Interfacial and Electrical Properties of GaAs Metal–Oxide–Semiconductor Capacitor by Using Fluorine-Plasma-Treated Interfacial Passivation Layer

ZrON gate-dielectric GaAs metal–oxide–semiconductor capacitors with a LaSiON interfacial passivation layer (IPL) and different fluorine-plasma-treatment methods are fabricated and investigated. Compared to using plasma-treating a GaAs surface or no plasma treatment, the sample with plasma-treated IPL exhibits the lowest interface-state density ( ${1.08 \times 10^{12}}$ cm−2eV−1), highest ${k}$ value (18.3) and smallest gate-leakage current ( ${1.62 \times 10^{-5}}$ A/cm2 at ${V_{fb}}$ + 1 V). The fact that plasma-treating IPL can effectively reduce the defect-related Ga/As–O and As–As bonds at GaAs surface and also incorporate more F into the gate stack to passivate the defects in it and at/near IPL/GaAs interface should be responsible for these.

Improved Interfacial and Electrical Properties of GaAs MOS Capacitor With LaON/TiON Multilayer Composite Gate Dielectric and LaON as Interfacial Passivation Layer

GaAs metal–oxide–semiconductor capacitors are fabricated by alternately depositing La oxynitride (LaON)/TiON or TiON/LaON or first depositing a LaON interlayer and then alternately depositing LaON/TiON, and their interfacial and electrical properties are investigated and compared. Experimental results show that the sample with LaON interlayer exhibits better interface quality and electrical performance than the other two samples: lower interface-state density ( $1.05 \times 10^{12}$ cm $^{-2}$ eV $^{-1})$ , smaller gate leakage current ( $2.33 \times 10^{-5}$ A/cm2 at $\text{V}_{\mathrm {fb}} + 1$ V), larger equivalent dielectric constant (25.3), and better high-field reliability. The involved mechanism lies in the fact that the LaON interlayer on the GaAs surface can effectively reduce the defective states at/near the interface by blocking the Ti/O in-diffusion and As/Ga out-diffusion, thus improving the interfacial and electrical properties of the device.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer**Supported by the National Natural Science Foundation of China under Grant Nos 61176100, 61274112 and 61404055.

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor (MOS) capacitors with or without ZrAlON as the interfacial passivation layer (IPL) are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAlON IPL exhibits better interfacial and electrical properties, including lower interface-state density ( cm−2eV−1), smaller gate leakage current ( A/cm2 at +1 V), smaller capacitance equivalent thickness (1.5 nm), and larger k value (26). The involved mechanisms lie in the fact that the ZrAlON IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interfacial Ga-/As-oxides and As-As dimers, which leads to improved interfacial and electrical properties for the devices.

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal–oxide–semiconductor capacitor

In this study, GaAs metal–oxide–semiconductor (MOS) capacitors using Y‐incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 × 1011 cm–2 eV–1), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 × 10–5A/cm2 at Vfb + 1 V). These merits should be attributed to the complementary properties of Y2O3 and Ta2O5:Y can effectively passivate the large amount of oxygen vacancies in Ta2O5, while the positively‐charged oxygen vacancies in Ta2O5 are capable of neutralizing the effects of the negative oxide charges in Y2O3. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. Capacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.magnified imageCapacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.

Reliability of Passivated and Unpassivated High-k Dielectric/GaAs Metal-Oxide-Semiconductor Capacitors

Metal-oxide-semiconductor (MOS) capacitors were fabricated using zirconium dioxide as a high-k dielectric layer on p-GaAs substrates with and without passivation layers. Ultrathin (1.8 nm) InP and ZnO were used as a passivation layer to prevent Fermi level pinning and regrowth of GaAs-native oxides at the interface between GaAs and ZrO2. The trapping of charge carriers and device reliability were investigated in passivated and unpassivated GaAs MOS capacitors during electrical stress. The improved characteristics in terms of stress-induced interface trap variation, hysteresis voltage, stress induced leakage current, and flat-band voltage have been demonstrated in InP and ZnO passivated MOS devices. Time dependent dielectric breakdown properties were studied in presence of electrical stress. The breakdown time was found to be 1748 and 1703 s in InP and ZnO passivated devices, respectively, however, in unpassivated devices, it was 928 s. The InP passivated GaAs MOS devices show improved electrical and breakdown characteristics over other MOS devices.

Self-Cleaning and Electrical Characteristics of ZrO2 (HfO2)/GaAs MOS Capacitor Fabricated by Atomic Layer Deposition

The reduction of native oxides on GaAs substrates is studied by short time pulsing of the metal precursor for self-cleaning mechanism using atomic layer deposition (ALD) of Trimethyl aluminum (TMA). The short time pulsing of the TMA is effective for self-cleaning mechanism to reduce the GaAs native oxides. X-ray photoelectron studies demonstrated that the pulsed deposition of TMA in the range of 2 to 4s is the most effective way of cleaning the GaAs native oxides. Microscopic studies clearly demonstrate the sharp interface between dielectric/GaAs. GaAs based metal oxide semiconductor (MOS) capacitors were fabricated with ZrO2 and HfO2 gate dielectrics using ALD. The effect of growth temperature of dielectric films on GaAs was studied. The as deposited samples have a significant amount of fixed charge in the bulk of the gate dielectric and at dielectric/semiconductor (ZrO2 or HfO2/GaAs) interface, which causes the flat band shift and frequency dispersion.

Interfacial characteristics of Al/Al2O3/ZnO/n-GaAs MOS capacitor

The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal—oxide—semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C–V curves. It is found that the ZnO layer can effectively improve the interface quality

Role of ultra thin pseudomorphic InP layer to improve the high-k dielectric/GaAs interface in realizing metal-oxide-semiconductor capacitor

In this article, we report GaAs metal-oxide-semiconductor (MOS) capacitors with a metal organic chemical vapor deposited ultrathin (1.5 nm) pseudomorphic InP interface passivation layer (IPL) and a thin (5 nm) ZrO2 high-k dielectric. Reduction of the surface states on InP passivated GaAs surfaces was observed from the photoluminescence study. The x-ray photoelectron spectra confirmed the dramatic reduction of GaAs native oxides (Ga-O and As-O) from the interface of ZrO2 and p-GaAs, implying that the Fermi level at the high-k/GaAs interface can be unpinned with good interface quality. As a result, very low values of interface trap density (1.1 × 1011 cm−2 eV−1) and hysteresis (8.21 mV) were observed. The same was done for directly deposited ZrO2 on GaAs surface to understand the efficacy of InP interface passivation layer on GaAs MOS devices. A systematic capacitance-voltage and current density-voltage studies were performed on bothAl/ZrO2/InP/p-GaAs and Al/ZrO2/p-GaAs structures. It was found that insertion of 1.5 nm InP ultrathin layer in-between ZrO2 and GaAs improves the essential parameters of GaAs MOS such as dielectric constant, frequency dispersion, leakage current, etc. The dielectric reliability has been studied with constant voltage stressing. A very small flatband voltage shift with stress time was observed in InP passivated GaAs MOS capacitors.

Influence of post deposition annealing on Y2O3-gated GaAs MOS capacitors and their reliability issues

The feasibility of employing yttrium oxide (Y2O3) as high-k gate dielectrics for GaAs metal-oxide-semiconductor (MOS) devices has been investigated. MOS capacitors were fabricated using RF-sputtered deposited Y2O3 films on NH4OH treated n-GaAs substrate. Indeed high-k (Y2O3)/GaAs MOS capacitors exhibiting fairly good electrical characteristics, for instance, especially low leakage current density, low hysteresis and allowable density of interface states, have been achieved. The effects of several annealing treatments on Y2O3-gated GaAs MOS capacitors have been investigated in order to optimize the process conditions. A decrease in accumulation capacitance (Cacc) following PDA effectively increases the equivalent oxide thickness (EOT), which is predicted to be correlated with the growth and continuous increase in the physical thickness of a lower-k inter-layer sandwiched between Y2O3 and GaAs. However, leakage currents and interface trap densities are reduced with higher values of annealing temperature. The variation of current density with an equivalent oxide thickness (EOT) has also been investigated.

Impact of Semiconductor and Interface-State Capacitance on Metal/High-k/GaAs Capacitance–Voltage Characteristics

The frequency dispersion of the maximum capacitance of GaAs metal-oxide-semiconductor (MOS) capacitors is studied. The frequency dispersion behavior observed in the capacitance-voltage characteristics of GaAs MOS capacitors is a result of low semiconductor capacitance and an interface-state capacitance that varies with frequency. The traditional approach for calculating interface-state capacitance does not result in frequency dispersion of the maximum capacitance. An interface-state capacitance model based on an extremely high number of interface states in a thin disordered interfacial region is presented to explain the frequency dispersion behavior. The model shows an excellent match with the experimental results. The model also suggests that maximum capacitance values in low-frequency capacitance-voltage characteristics may be determined by the capacitance associated with the interface traps rather than the semiconductor charge and does not necessarily indicate the presence of free carriers.

Fabrication and Characterization of GaAs MOS Capacitor With CVD Grown Polymer-Based Thin Film as a Gate Dielectric

GaAs Metal-Oxide-Semiconductor (MOS) capacitor using a polymer-based thin film as a gate dielectric has been fabricated and electrically characterized. The influence of the atomic concentration of oxygen in the dielectric films on the capacitance-voltage (C-V) and current-voltage characteristics of the MOS capacitors has been thoroughly investigated. The GaAs MOS capacitor obtained at low concentration of oxygen showed an almost ideal MOS capacitor behavior. The density of the interface traps extracted from the conductance-frequency measurement was found to be as low as 9.7 x 109 eV-1 cm-2. In addition, the MOS capacitor exhibits very low leakage current (6.6 10-9 A/cm2 at -1 V) and relatively high breakdown voltage (2.05 MV/cm). These characteristics make polymer-based thin films very attractive as a passivation layer and a gate dielectric for GaAs MOSFET. The ability to tune the polymer through chemical synthesis and polymer functionalization makes CVD grown polymer-based thin films very promising for the passivation of virtually any semiconductor surface.

Low Leakage and High-k Liquid Phase Deposited TiO[sub 2] and SiO[sub 2]/TiO[sub 2] Films on (NH[sub 4])[sub 2]S-Treated GaAs

High bandgap SiO 2 on TiO 2 films prepared by liquid phase deposition can lower the thermionic emission leakage from the low bandgap TiO 2 on GaAs metal-oxide-semiconductor (MOS) structure. Furthermore, (NH 4 ) 2 S treatment improves the TiO 2 /GaAs interface quality. The leakage current densities of TiO 2 on the (NH 4 ) 2 S-treated GaAs MOS capacitor are 6.8 × 10- 6 and 1.2 × 10 ―5 A/cm 2 at ±0.5 MV/cm, respectively. The dielectric constant is ∼47. With liquid phase deposited SiO 2 /TiO 2 films as dielectrics, the leakage current densities can be improved to 2.4 × 10 ―7 and 4.3 × 10 ―7 A/cm 2 at ±0.5 MV/cm, respectively. The effective dielectric constant can reach ∼44.

Self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor field-effect transistor with Al2O3 gate dielectric

In this letter, we report fabrication of self-aligned inversion-type enhancement-mode GaAs metal-oxide-semiconductor (MOS) field-effect transistors with atomic layer deposition of Al2O3 gate dielectric directly on GaAs substrates using a simple ex situ wet clean of GaAs. Thermal stability of the gate stack was examined by monitoring the frequency dispersion behavior of GaAs MOS capacitors under different annealing conditions. A maximum drive current of ∼4.5μA∕μm was obtained for a gate length of 20μm at a gate overdrive of 2.5V. The threshold voltage and subthreshold slope were determined to be ∼0.4V and ∼145mV∕dec from the corresponding Id-Vg characteristics.

Flatband voltage instability characteristics of HfO2-based GaAs metal-oxide-semiconductor capacitors with a thin Ge layer

This work investigates the flatband voltage instability of HfO2-based GaAs metal-oxide-semiconductor (MOS) capacitor with a thin germanium (Ge) interfacial passivation layer (IPL). Both positive and negative dc gate biases are used as stress condition. By studying various samples such as the devices with extremely thin equivalent oxide thickness of 8.7Å, with optimum, thick Ge IPLs, and without Ge IPL at a given HfO2 thickness, as well as the devices with varying thicknesses of HfO2 on the optimum Ge IPLs, it is found that both the interface trap and the bulk trap of HfO2 are crucial in affecting the flatband voltage instability characteristics of HfO2 GaAs MOS capacitors. The results indicate that the minimum flatband voltage instability requires a higher quality interface and a thinner HfO2 layer, which can be achieved by employing Ge IPL technique in GaAs system.

Metal-oxide-semiconductor capacitors on GaAs with germanium nitride passivation layer

We present gallium arsenide (GaAs) metal-oxide-semiconductor capacitors (MOSCAPs) with a thin HfO2 gate dielectric and a thin germanium nitride (GexNy) interfacial passivation layer (IPL). TaN∕HfO2∕GexNy∕GaAs MOSCAPs show a low interface state density and a thin equivalent oxide thickness (1.6nm). Compared to GaAs MOSCAPs with germanium (Ge) IPL, the GexNy IPL has a smaller slow trap density, which is confirmed by improved C-V characteristics without humps near the flatband voltage. The lower rate of flatband voltage shift and gate leakage decreasing under constant gate voltage stress were also demonstrated in GaAs MOSCAPs with GexNy IPL than the Ge IPL.

GaAs metal-oxide-semiconductor device with HfO2∕TaN gate stack and thermal nitridation surface passivation

Oxides induced Fermi level pinning at the interface between the GaAs and high-k gate dielectric is a major obstacle for developing high performance GaAs metal-oxide-semiconductor (MOS) devices. In this letter, thermal nitridation treatment on GaAs surface prior to the high-k deposition is proposed to solve the issue of interface pinning. It is found that an optimized nitride layer formed during the thermal nitridation surface treatment can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and HfO2. By using thermal nitridation treatment and in situ metal-organic chemical vapor deposition HfO2 as high-k gate dielectric, GaAs MOS capacitor with improved capacitance-voltage characteristics and reduced gate leakage current is achieved.