Future Field Programmable Gate Arrays Research Articles

Soft Processors as a Prospective Platform of the Future

Modern field-programmable gate arrays (FPGA) play a very important role in designing of new soft CPUs and integrated systems-on-chips. Compared to an application-specific integrated circuit (ASIC), FPGAs provide the highest degree of flexibility being almost fully application neutral. The price of such flexibility is higher usage of basic logic gates and decrease in circuit operating frequency caused by the use of switched interconnect fabric as opposed to fixed metal interconnect defined by masks at manufacturing for ASIC.However due to more regular and less complex FPGA structure they lead in terms of new IC manufacturing technologies adoption. Therefore we can expect next generation of general purpose FPGA devices based on 14nm norms in 2017.This article examines the applicability of Moore's Law to general purpose FPGAs, using datum for Xilinx Spartan and Altera Cyclone families. On the basis of the obtained data the conclusion that in the near future FPGAs become a prospective platform for general purpose CPUs implementation is drawn.

FPGA based architecture of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR)

Passive Bistatic Radar (PBR) exploits existing signals of opportunity from different sources such as Radio and TV signals. Extensive Cancellation Algorithm (ECA) has been proven to be a very effective way to mitigate the effects of direct signal, multipath and clutter echoes in PBR. Also, it is able to detect a moving target accurately when it comes to strong-clutter environment and long-range detection providing evidence for its robustness. However, ECA is a computationally intensive algorithm and will benefit from parallel processing and modern computational platforms such as Field Programmable Gate Arrays (FPGAs). This work involves transformation of ECA by exploring opportunities for parallel processing and elimination of any unnecessary computations and storages. ECA algorithm has been also implemented on FPGAs for high speed computation by exploiting parallel and pipelining approaches. A new software tool called Radar Signal Processing Tool (RSPT) has been developed. It allows the designer to auto-generate fully optimized VHDL representation of ECA by specifying many user input parameters through GUI. The produced VHDL code is independent of FPGA part. It is also appropriate for use with any future high performance FPGAs or ASICs to further cut down computation time. Moreover, it provides the designer a feedback on various performance parameters. This offers the designer an ability to make any adjustments to the ECA component until the desired performance of the overall System on Chip (SoC) is achieved. The computation time of our transformed/optimized algorithm has improved by a factor of 3.8. Its FPGA implementation offers a speed up of 18 over CPU.

“Our Original 3D Idea Still Has To Happen; And It Will”

Ivo Bolsens is senior vice president (SVP) and chief technology officer (CTO) at Xilinx, a leading supplier of field-programmable gate arrays (FPGAs). At Xilinx, he is responsible for advanced technology development, as well as the company's research laboratories and university program. Design & Test's Erik Jan Marinissen met with Dr. Bolsens in November 2012 during the IEEE International Test Conference in Anaheim, CA,USA, where Bolsens was the opening keynote speaker at the co-located 3D-TEST Workshop . Shortly prior to his keynote talk, this interview took place during lunch at a Disneyland restaurant, covering Bolsens' career from IMEC to Xilinx, current and future FPGAs, the differences between research and company environments, and Xilinx recent 3D-FPGA product.

Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs

As new nonvolatile memory technologies become increasingly mature, there has been a growing interest on investigating their use in future field-programmable gate arrays (FPGAs). Similar to existing FPGAs with embedded Flash memory, future FPGAs can embed these new nonvolatile memories to persistently store configuration data. By comparing with prior work, we first propose the more appropriate design style for new nonvolatile configuration data storage memory. Moreover, this brief studies a dynamic random-access memory (DRAM)-based FPGA design strategy enabled by high-density embedded nonvolatile memory. Existing FPGAs do not use on-chip DRAM cells for configuration data storage mainly because DRAM self-refresh involves destructive DRAM read. This problem can be solved, if we use embedded nonvolatile memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Analysis and simulations have been carried out to demonstrate the potential advantages of such a design strategy.

Fault tolerance and reliability in field-programmable gate arrays

Reduced device-level reliability and increased within-die process variability will become serious issues for future field-programmable gate arrays (FPGAs), and will result in faults developing dynamically during the lifetime of the integrated circuit. Fortunately, FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome such degradation-induced faults. This study provides a comprehensive survey of fault detection methods and fault-tolerance schemes specifically for FPGAs and in the context of device degradation, with the goal of laying a strong foundation for future research in this field. All methods and schemes are quantitatively compared and some particularly promising approaches are highlighted.

Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect

The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54% improvement in area-delay product over the best performing architecture with standard copper interconnect in 22 nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43% over FPGAs implemented using traditional copper interconnect in future process technologies.

High performance reconfigurable computing

High performance reconfigurable computing

Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

It has become clear that large embedded configurable memory arrays will be essential in future field programmable gate arrays (FPGAs). Embedded arrays provide high-density high-speed implementations of the storage parts of circuits, Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided. This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as multioutput ROMs, and used to implement logic, In this paper, we describe two versions of a new technology mapping algorithm that identifies parts of circuits that can be efficiently mapped to an embedded array and performs this mapping, The first version of the algorithm places no constraints on the depth of the final circuit; on a set of 29 sequential and combinational benchmarks, the tool is able to map, on average, 59.7 4-LUTs into a single 2-Kbit memory array, while increasing the critical path by 7%, The second version of the algorithm places a constraint on the depth of the final circuit; it maps, on average, 56.7 4-LUTs into the same memory array, while increasing the critical path by only 2.3%. This paper also considers the effect of the memory array architecture on the ability of the algorithm to pack logic into memory, It is shown that the algorithm performs best when each array has between 512 and 2048 bits, and has a word width that can be configured as 1, 2, 4, or 8.