Fundamental Voltage-controlled Oscillator Research Articles

A 60 GHz low phase noise VCO with second harmonic tail extraction in 40-nm CMOS

This work presents a 60 GHz continuously adjustable mm-wave cross-coupled voltage − controlled oscillator (VCO) utilizing an innovative frequency doubling technique in 40 nm CMOS technology. The extraction of the second harmonic is performed through a transformer from the tail of the 30 GHz fundamental VCO. The primary side of the transformer serves a dual purpose, functioning both as a filter for the second harmonic and as a balun simultaneously. The circuit incorporates a MOS varactor along with a four-bit binary weighed capacitor bank to achieve coarse and fine frequency tuning respectively. Post Layout simulation results indicate that the VCO spans a broad tuning range of 12.3 GHz, covering frequencies from 52.7 to 64.98 GHz. Phase noise (PN) remains below −96.3 dBc/Hz at a 1 MHz frequency offset within all bands Power consumption, including the output stage, is 21.8 mW from a 1.1-Volt supply. The VCO provides more than −13 dBm output power in all frequency bands and occupies a chip area of 0.53 mm2.

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS

The minimal achievable phase noise (PN) of millimeter-wave (mm-wave) voltage-controlled oscillators (VCOs) is bounded by the smallest realizable inductor with a reasonable high quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> ). A multi-core VCO reduces the total equivalent inductance of the tank by synchronizing multiple VCO cores, therefore improving the PN performance. This article presents a 60-GHz fundamental VCO based on a mode-rejection circular triple-coupled-transformer tank, which improves the PN performance of the VCO from three aspects. 1) the circular topology improves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> of small inductors in the mm-wave frequency range by alleviating the inner edge deconstructive coupling; 2) compared with the circular inductor topology, the triple-coupled transformer provides the flexibility to suppress the unwanted oscillation mode at the center taps of the gate coils, which enables the NMOS-only VCO configuration to avoid PN degradation due to limited PMOS performance in the mm-wave frequency range; and 3) the triple-coupled transformer boosts the gate-to-source voltage swing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{m}$ </tex-math></inline-formula> transistors. The quad-core VCO prototype is designed and fabricated in a 65-nm CMOS process. It achieves a measured PN of –104.7 dBc/Hz at 1-MHz offset and a corresponding figure of merit (FoM) of 186.5 dBc/Hz at 59.1-GHz carrier frequency.

Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS

This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO) in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for phase noise reduction while maintaining low voltage swings for reliability. In the multi-core configuration, the oscillators are coupled in a way that also simplifies LO distribution toward the transmitter and receiver. The potential parasitic modes that occur both in single-core and multi-core configurations are suppressed by design. The implicit common-mode (CM) impedance control is utilized to reduce phase noise without any large extra tail inductor as used in a conventional complementary oscillator. The distributed nature of energy restoring elements in the proposed stacked oscillator also offers robust parasitic mode suppression compared to alternative implementation based on a conventional complementary oscillator. The working range of the prototype is between 55 and 63 GHz corresponding to a tuning range of 13.4% with power consumption varying from 15.3 to 12 mW across the tuning range. The prototype achieves the best phase noise of −95 and −121.7 dBc/Hz at 1- and 10-MHz offsets from the carrier at 55GHz. The corresponding peak figure of merits (FOMs) achieved are 178 and 185 dBc/Hz at 1- and 10-MHz offsets from the carrier.

A noise circulating VCO with an intrinsic injection locking tripler

AbstractA noise circulating voltage‐controlled oscillator (VCO) with an intrinsic injection locking tripler is introduced. Based on the conventional frequency tripling scheme, by integrating the injection transistor pair into the fundamental VCO core, the current of the fundamental VCO core is reused by the injection transistor pair, and the phase noise is reduced due to the noise circulating behavior. The proposed VCO may achieve the fundamental and 3rd harmonic outputs, simultaneously. A protype design is implemented in a standard 65 nm CMOS process, with a tuning range of 33.68–40.11 GHz (17.4%). The phase noise at 1‐MHz offset varies between −101.2 and −97.9 dBc/Hz among the tuning range. The FoMT is in the range of 190.4 and 187.9 dBc/Hz, at 1‐MHz offset.

A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications

ABSTRACT A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to . The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than – 12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies.

W- and G-Band GaN Voltage-Controlled Oscillators With High Output Power and High Efficiency

This article presents W- and G-band voltage-controlled oscillators (VCOs) fabricated in a 60 nm GaN high electron-mobility transistor (HEMT) process with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> of 190/250 GHz. Two W-band fundamental VCOs (VCO1 and VCO2) are designed without and with a varactor, respectively. In addition, a G-band push-push VCO (VCO3) is designed to demonstrate feasibility of a GaN power source in the sub-terahertz band. The measurement shows that VCO1 and VCO2 exhibit output power of 22.5 and 22.6 dBm and dc-to-RF efficiency of 14.7% and 16.8% at 87.5 and 86.5 GHz, respectively. The power and efficiency are the highest values among the previously reported GaN VCOs operating beyond 50 GHz. Furthermore, VCO2 achieves a wide tuning range of 9.0 GHz (77.5-86.5 GHz). The VCO3 exhibits high output power of 9.3 dBm at 180.6 GHz. To the best of the authors' knowledge, this is the first demonstration of a G-band VCO in a GaN technology. The W- and G-band VCOs occupy compact chip areas of 0.48 and 0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

A 77-GHz High Gain Low Noise Receiver for Automatic Radar Applications

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

A Compact Harmonic Radar System With Active Tags at 61/122 GHz ISM Band in SiGe BiCMOS for Precise Localization

This article presents a frequency-modulated continuous wave (FMCW) harmonic radar in the 61-/122-GHz industrial, scientific, and medical (ISM) frequency bands. The radar is based on two self-designed monolithic microwave wave integrated circuits (MMICs) for the transceiver (TRX) and tag which are fabricated in a 130-nm SiGe BiCMOS technology. The presented TRX-MMIC consists of a fundamental voltage-controlled oscillator (VCO), a power amplifier (PA), Wilkinson power dividers, and a static divide-by-16 chain for stabilization within a phase-locked loop (PLL) in the transmitter (TX) part. The receiver (RX) part has two channels with a low noise amplifier (LNA), a Gilbert cell mixer, and an intermediate frequency (IF)-amplifier each. The fundamental of the VCO is converted by a frequency doubler and distributed to the local oscillator (LO) input of the RX-mixers. With such a TRX architecture the active nonlinear tag which consists of antennas, pre-amplifiers, and a frequency doubler can be detected. For a sweep from 60 to 64 GHz, a spatial resolution of 4 cm at 1-m distance and a range of 23.3 m is achieved. With these characteristics, the tag enables harmonic radar applications in the millimeter-wave (mm-wave) range for medium range with high accuracy and resolution with a small form factor.

A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications

This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divide-by-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of −94.7 dBc/Hz at the 1-MHz offset and an output power of −3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of $2.7\times3.1$ mm2.

A 170-GHz 23.7% Tuning-Range CMOS Injection-Locked LO Generator With Third-Harmonic Enhancement

This article proposes a harmonic-extraction technique to enhance the amplitude and the phase noise of LC oscillators at the third-harmonic frequency. By leveraging this technique, a cascaded subterahertz (sub-THz) injection-locked local oscillator (LO) generator is proposed, which consists of a fundamental voltage-controlled oscillator (VCO) and a millimeter-wave (mm-wave) injection-locked frequency multiplier (ILFM). Fabricated in a 65-nm CMOS process, the VCO prototype concurrently generates two output signals: the first output at the fundamental frequency from 17.1 to 21.7 GHz with a 10-MHz-offset phase noise from −120.6 to −126 dBc/Hz, the second output at the third-harmonic frequency from 51.3 to 65.1 GHz with a 10-MHz-offset phase noise of −116.3 dBc/Hz, and the third-harmonic output power of −19.1 dBm. The VCO prototype consumes 1.4 mW from a 0.3-V supply, resulting in an FoM from −186 to −189.6 dBc/Hz at the fundamental frequency. The sub-THz injection-locked LO generator achieves a frequency tuning range of 23.7% from 153.9 to 195.3 GHz with a 10-MHz-offset phase noise of −106.8 dBc/Hz and the output power of −14.6 dBm, and consumes 8.4 mW, which corresponds to an FoM of −181.2 dBc/Hz and an ${\mathrm {FoM}}_{T}$ of −188.7 dBc/Hz at 153.9 GHz.

A WR-3 Band Fundamental Voltage-Controlled Oscillator With a Wide Frequency Tuning Range and High Output Power

This paper presents a 300-GHz voltage-controlled oscillator (VCO) with a wide frequency tuning range and high output power. To generate fundamental oscillation at 300 GHz, a cascode cross-coupled pair is employed as a VCO core instead of a conventional common-emitter pair. Capacitive emitter degeneration is added to the VCO core to achieve a wide bandwidth of a negative conductance. In addition, the phase of the oscillation feedback loop is analyzed and optimized to further extend the tuning range. The VCO is fabricated in a 0.25- $\mu \text{m}$ InP DHBT technology ( $f_{\mathrm {T}}/f_{\mathrm {max}} = 392$ /859 GHz). Measurements show that the VCO frequency is tuned from 272.4 to 310.8 GHz with a peak output power of 1.5 dBm. To the best of authors’ knowledge, this is the widest tuning range of 38.4 GHz (a fractional bandwidth of 13.2%) among the reported fundamental VCOs at the WR-3 band.

W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

A SiGe Highly Integrated FMCW Transmitter Module With a 59.5–70.5-GHz Single Sweep Cover

A fully integrated wide-bandwidth transmitter (TX) module intended for use in short-range frequency-modulated continuous-wave radar applications is proposed. By incorporating an on-chip fractional- ${N}$ phase-locked loop based on the fundamental voltage-controlled oscillator, the TX is able to synthesize highly programmable 11-GHz linear chirps around the 65-GHz central frequency, hence theoretically enabling sub-1.5-cm spatial resolutions. Implemented in a 0.13- $\mu \text {m}$ BiCMOS process, the test-chip delivers more than +5 dBm of output power and achieves the measured root-mean-square ramp error (nonlinearity) of 340 kHz for a 60-GHz/ms modulation rate signal over the complete range of interest. The presented TX module dissipates 550mW and also includes an adequate on-board directional $4\times4$ antenna array.

A 61-GHz SiGe Transceiver Frontend for Energy and Data Transmission of Passive RFID Single-Chip Tags With Integrated Antennas

This paper presents SiGe-based transmitter and receiver chips for a radio frequency identification (RFID) frontend in the 61-GHz industrial, scientific, and medical (ISM) frequency band. The chips are fabricated in a modern 130-nm SiGe BiCMOS technology with HBTs offering an $f_{T}$ of 250 GHz and $f_{\mathrm{max}}$ of 370 GHz. The presented transmitter consists of a fundamental voltage-controlled oscillator (VCO), a power amplifier (PA), lumped element Wilkinson power dividers, and a static divide-by-16 chain for stabilization within a phase-locked loop (PLL). Two variants of the transmitter are fabricated with supply voltages of 3.3 and 5 V, respectively. The transmitters are designed to provide an efficient signal source to supply a passive RFID tag with the maximum allowed 20-dBm effective isotropic radiated power (EIRP) for short-range devices. The 3.3-V transmitter chip achieves a peak output power of 17 dBm, PAEPA of 18.6% and dc-to-RF efficiency of 12.9% (excluding the divider). At 61 GHz, a phase noise of −102 dBc/Hz at 1 MHz offset is achieved. The power consumption for the 5- and 3.3-V transmitter chips is 710 and 482 mW, respectively. The receiver chip is implemented as two Gilbert cell mixers in-phase quadrature configuration to compensate for destructive interference that may be caused by varying distance between reader and tag.

High-Efficiency Millimeter-Wave Single-Ended and Differential Fundamental Oscillators in CMOS

This paper reports an approach to designing compact high-efficiency millimeter-wave fundamental oscillators operating above the $f_{\text {max}}/2$ of the active device. The approach takes full consideration of the nonlinearity of the active device and the finite quality factor of the passive devices to provide an accurate and optimal oscillator design in terms of the output power and efficiency. The 213-GHz single-ended and differential fundamental oscillators in 65-nm CMOS technology are presented to demonstrate the effectiveness of the proposed method. Using a compact capacitive transformer design, the single-ended oscillator achieves 0.79-mW output power per transistor (16 $\mu \text{m}$ ) at 1-V supply and a peak dc-to-RF efficiency of 8.02% ( $V_{\mathrm{ DD}}=0.80$ V) within a core area of 0.0101 mm2, and a measured phase noise of −93.4 dBc/Hz at 1-MHz offset. The differential oscillator exhibits approximately the same performance. A 213-GHz fundamental voltage-controlled oscillator (VCO) with a bulk tuning method is also demonstrated in this paper. The measured peak efficiency of the VCO is 6.02% with a tuning range of 2.3% at 0.6-V supply.

A W-Band Low-Noise PLL With a Fundamental VCO in SiGe for Millimeter-Wave Applications

A W-band fundamental phase-locked loop (PLL) is designed and fully integrated to achieve high output power and low noise in a 0.13-μm SiGe BiCMOS process. A PLL with a fundamental voltage-controlled oscillator (VCO) is chosen after comparing several frequency-synthesizer architectures. Local oscillator (LO) generation and LO distribution are also considered. The employed free-running VCO achieves a tuning range from 92.5 to 102.5 GHz (8.3%), an output power of 6 dBm, and a phase noise of -124.5 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 92.7 to 100.2 GHz, and the phase noise is -102 dBc/Hz at 1-MHz offset. The root mean square jitter integrated from 1 MHz to 1 GHz is 71 fs. Finally, the figure-of-merit for VCOs is discussed.

(Invited) Combining SiGe BiCMOS and InP Processing in an on-top of Chip Integration Approach

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs.Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b).To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2).Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes.

Integrated wideband and low phase‐noise signal source using two voltage‐controlled oscillators and a mixer

This study presents a method to design a wideband signal source based on two voltage-controlled oscillators (VCOs) with different centre frequencies and a mixer. The principle is to combine three frequency bands to form one wide frequency range. The three bands consist of second harmonic bands from two VCOs and a mixer band that is generated by mixing the two fundamental signals of VCOs to bridge the frequency gap. Apart from the wide tuning range, an additional benefit of a mixer-based signal source is that the phase-noise increases ∼3 dB/octave, which is less than the theoretical limit (6 dB/octave) for a fundamental frequency VCO followed by a frequency multiplier or extraction of second harmonic signal from a VCO. A prototype of the proposed signal source implemented in indium gallium phosphide hetero junction bipolar transistor monolithic microwave integrated circuit technology demonstrates both wide frequency tuning range and a very low phase noise. It exhibits a tuning bandwidth extending from 11.8 to 16.7 GHz and the signal's phase noise varies between −91 and −103 dBc/Hz at 100 kHz offset frequency.