Fundamental-frequency Positive-sequence Component Research Articles

Enhanced PLL-less grid synchronization algorithm amidst unbalanced and distorted three-phase grid conditions

Fast and precise tracking of grid voltage attributes is essential for the smooth and reliable control and operation of grid-side converters. The synchronous reference-frame phase-locked loop (SRF-PLL) approach is commonly used for this purpose, although it has issues related to the stability limit and sluggish transient response. Consequently, PLL-less grid synchronization approaches are becoming increasingly prevalent. In this context, in the present paper, a discrete Fourier transform-based band pass filter (DFT-BPF) is designed in the prefiltering stage for the purpose of extracting the fundamental frequency positive sequence component (FFPS) from unbalanced and distorted grid conditions. Despite being widely used, the SRF-PLL is struggling with stability issues and demands tedious tuning effort. For this objective, a simple frequency estimator has been developed, which is capable of accurately estimating the fundamental frequency. Additionally, a curve fitting based error correction technique is employed to adaptively estimate the amplitude and phase-angle of the fundamental component without using frequency feedback loop. The experimental results validate the efficacy of the proposed scheme.

Modified <italic>pq</italic>-Theory-Based Control of Solar-PV-Integrated UPQC-S

This paper proposes a modified pq-theory-based control of a solar photovoltaic (PV)-array-integrated unified power quality conditioner (PV-UPQC-S). The system incorporates clean energy generation along with power quality improvement, thus increasing functionality of the system. The fundamental-frequency positive-sequence components of voltages at the point of common coupling (PCC) are extracted using the generalized cascaded delay signal cancellation technique, which are then used in pq-theory-based control to estimate reference signals for the PV-UPQC-S. This modification in pq theory enables its application for PV-UPQC-S control under conditions of distorted PCC voltages. The series voltage-source converter (VSC) of the PV-UPQC-S operates such that it shares a part of the reactive power of the load even under nominal grid conditions. This increases the utilization of the series VSC while reducing the rating of shunt VSC. The PV array is integrated at the dc bus of the UPQC and provides a part of active load power, thus reducing demand on the supply system. The dynamic performance of the modified pq-theory-based PV-UPQC-S is verified by simulating the system in MATLAB-Simulink with a combination of linear and nonlinear loads. The steady-state and dynamic performances of the system are then experimentally validated through extensive testing on a scaled-down laboratory prototype.

Capability evaluation of four-leg DSTATCOM for compensating multifarious loads

A four-leg distribution static compensator (FL-DSTATCOM) has been investigated to achieve harmonic elimination, supply current balancing, compensation of reactive power and current in the neutral conductor of a three-phase, four-wire distribution system with various types of static, dynamic and combined loads. The capability of FL-DSTATCOM for compensating reactive power under dynamic condition is evaluated with induction machine having variable load torque. Also, the performance of FL-DSTATCOM is evaluated with combined load, which is a combination of dynamic and unbalanced static loads. The FL-DSTATCOM injects reactive and harmonics components of load current extracted using synchronous reference frame theory. With FL-DSTATCOM, the unbalanced, harmonic and reactive loads will appear to the main power supply as balanced, linear and unity power factor load. Hence, the main power supply would deliver only fundamental frequency positive sequence components of load current. The switching pulses are generated by employing hysteresis current controller. MATLAB/SIMULINK has been used for capability evaluation under multifarious loading conditions considering IEEE standard 519. The simulation results prove that the FL-DSTATCOM is capable of making the supply current as balanced and sinusoidal, maintaining the PF at point of common coupling near to unity and reducing the supply neutral current very close to zero.

An Efficient Implementation of Generalized Delayed Signal Cancellation PLL

The phase, frequency, and amplitude of the fundamental-frequency positive-sequence component of the grid voltage are crucial information in control of most grid-connected power electronic based equipment. Often, a standard phase-locked loop (PLL) with a prefiltering stage is employed for the extraction of this information. Inspired by the concept of delayed signal cancellation (DSC), the generalized DSC (GDSC) operator has recently been introduced as an interesting option for the PLL prefiltering stage. In its typical structure, the GDSC operator extracts the grid fundamental component and feeds it to a conventional synchronous reference frame PLL (SRF-PLL). The frequency estimated by the SRF-PLL is then fed back to the GDSC operator to make it frequency adaptive. This structure, however, suffers from two main drawbacks: 1) the system is highly nonlinear, and therefore, it is difficult to ensure its stability under all circumstances; and 2) adapting the GDSC to grid frequency variations increases the implementation complexity and computational effort, particularly when the interpolation techniques are used for this purpose. To avoid these problems while maintaining high accuracy in the extraction of grid voltage quantities, an efficient and low-cost implementation of the GDSC-PLL is suggested in this paper. The proposed structure, which is called the enhanced GDSC-PLL (EGDSC-PLL), uses a nonadaptive GDSC operator as its prefiltering stage and corrects the phase-shift and amplitude scaling caused by this operator by using two units, called the phase-error compensator and amplitude-error compensator. The effectiveness of the EGDSC-PLL is confirmed through simulation and experimental results.

A novel control strategy for dynamic voltage restorer using decoupled multiple reference frame PLL (DMRF-PLL)

This paper presents a new control scheme for dynamic voltage restorer (DVR), which consists of a set of series and shunt converters connected back-to-back (BTB), three series transformers, and a dc capacitor installed on the common dc-link. The DVR is characterized by installing the shunt converter on the source side and the series converter on the load side. A decoupled multiple reference frame phase-locked-loop (DMRFPLL) is proposed, which decouples signals of different frequencies and eliminates interactions between the fundamental-frequency positive-sequence components and harmonic and/or negative-sequence components in the grid voltages. The proposed DMRF-PLL scheme achieves a fast, precise, and robust positive-sequence voltage detection even under unbalanced and/or distorted grid voltages conditions. A detailed description and derivation of the detection method is presented. Besides, a separate proportional-integral (PI) controller is adopted to regulate the dc-link capacitor voltage. The load voltage waveform is restored to be sinusoidal with fundamental frequency by dynamically injecting compensating voltages to the series brunch of converters. The validity and effectiveness of the presented scheme has been confirmed by extensive simulation results obtained from a 380V/50kVA system using Matlab/Simulink.

Multiple Reference Frame-Based Control of Three-Phase PWM Boost Rectifiers under Unbalanced and Distorted Input Conditions

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Many control algorithms and circuits for three-phase pulse width modulation active rectifiers have been proposed in the past decades. In most of the research, it is often assumed that the input voltages are balanced or contain only fundamental frequency components. In this paper, a selective harmonic compensation method is proposed based on an improved multiple reference frame algorithm, which decouples signals of different frequencies before reference frame transformation. This technique eliminates interactions between the fundamental-frequency positive-sequence components and harmonic and/or negative-sequence components in the input currents, so that fast and accurate regulation of harmonic and unbalanced currents can be achieved. A decoupled phase-locked loop algorithm is used for proper synchronization with the utility voltage, which also benefits from the multiple reference frame technique. The proposed control method leads to considerable reduction in low-order harmonic contents in the rectifier input current and achieves almost zero steady-state error through feedback loops. Extensive experimental tests based on a fixed-point digital signal processor controlled 2 kW prototype are used to verify the effectiveness of the proposed ideas. </para>

Decoupled Double Synchronous Reference Frame PLL for Power Converters Control

This paper deals with a crucial aspect in the control of grid-connected power converters, i.e., the detection of the fundamental-frequency positive-sequence component of the utility voltage under unbalanced and distorted conditions. Specifically, it proposes a positive-sequence detector based on a new decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL), which completely eliminates the detection errors of conventional synchronous reference frame PLL's (SRF-PLL). This is achieved by transforming both positive- and negative-sequence components of the utility voltage into the double SRF, from which a decoupling network is developed in order to cleanly extract and separate the positive- and negative-sequence components. The resultant DDSRF-PLL conducts then to a fast, precise, and robust positive-sequence voltage detection even under unbalanced and distorted grid conditions. The paper presents a detailed description and derivation of the proposed detection method, together with an extensive evaluation using simulation and experimental results from a digital signal processor-based laboratory prototype in order to verify and validate the excellent performance achieved by the DDSRF-PLL