Function Of Gate Oxide Thickness Research Articles

Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal–Oxide–Semiconductor Field Effect Transistors

In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Experimental evidence for nonlucky electron model effect in 0.15-μm NMOSFETs

It is shown that in 0.15-/spl mu/m NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-/spl mu/m NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.

Oxide thickness dependence of hole trap generation in MOS structures under high-field electron injection

Hole trapping in the gate oxide of MOS devices causes instabilities of device parameters and serious reliability problems in MOS transistors and memories. In this work, hole traps, generated by high-field electron injection, are studied in thermal oxides in the thickness range below 10 nm. PMOS transistors, after various doses of positive and negative FN injection and post-stress annealing are subjected to substrate hot hole injection to investigate hole trapping kinetics. Parameters of hole traps, generated under the stress, are studied as a function of gate oxide thickness and stress dose.

Characterization of Hole Traps Generated by Electron Injection in Thin SiO2 Films

ABSTRACTMOS device stability can be significantly affected by charge trapping in the gate oxide, which changes device parameters and causes serious reliability problems in transistors and memory cells. Hole traps, generated by high-field electron injection, are studied in this work in devices with thermal oxides less than 10 nm thick. PMOS transistors, after various doses of positive and negative Fowler-Nordheim injection and post-stress annealing, are subjected to substrate hot hole injection to investigate hole trapping kinetics. Parameters of hole traps, generated under the stress, are studied as a function of gate oxide thickness and electron injection dose.

Time dependence of interface trap formation in MOSFETs following pulsed irradiation

The time dependence of interference trap (N/sub it/) formation in MOSFETs was studied as a function of gate oxide thickness, oxide growth type, substrate orientation, temperature, and gate bias. Two different N/sub it/ formation mechanisms are observed. Most (typically 90%) of the formation, called the late process, occurs slowly at long times (1-10000 s) after the radiation pulse. From a variety of experimental data, it is concluded that the rate of the late process is limited by drift of a radiation-induced positive ion, probably H/sup +/, through the gate oxide to the Si-SiO/sub 2/ interface where the N/sub it/ are formed. A relatively fast, or early, process is responsible for a small percentage of the total N/sub it/ formation. The time constant for this process appears to be consistent with hole drift through the oxide. >

Correlation between Mechanical Stress and Hydrogen-Related Effects on Radiation-Induced Damage in MOS Structures

Correlation between mechanical stress and hydrogen effects on radiation damage in polycide-gate MOS capacitors was investigated as a function of gate-oxide thickness. The compressive stress magnitude was altered by varying the silicide (TiSi2 or WSi2) thickness in the polycide-gate electrode, and hydrogen introduction into gate-SiO2 film was carried out by diffusion from plasma-deposited silicon-nitride passivation film (SiN-Cap). In a MOS capacitor without passivation film (No-Cap sample), it was found that compressive stress on gate-SiO2 reduces both positive charge build-up (#x00394;Qot) and interface-trap generation (#x00394;Dit). Radiation induced shift, #x00394;Qot exhibits a smaller stress effect as compared witni #x00394;Dit. As gate-SiO2 thickness decreases, the stress effect on #x00394;Qot increases, while this effect on #x00394;Dit remains nearly constant. This compressive stress effect was inhibited by hydrogen diffusion, especially in #x00394;Dit. In addition, both stress effects on #x00394;Qot and #x00394;Dit in SiN-Cap samples show a gate-oxide Thickness dependence similar to that on #x00394;Qot in No-Cap samples. The stress effect observed in No-Cap samples can be explained on the basis of the bond reformation process at the SiO2/Si interface and near the electrode/SiO2 interface. In a SiN-Cap sample, hydrogen is highly distributed at the SiO2/Si interface region and hydrogen-related interface-trap generation may occur at this interface region. As a result, only the stress effect near the gate-electrode was observed in SiN-Cap samples.

Mechanical Stress Dependence of Radiation Effects in MOS Structures

The effects of mechanical stress on radiation damage in polycide-gate MOS capacitors have been investigated as a function of gate-oxide thickness and silicide-gate electrode material (TiSi2, MoSi2 and WSi2). It was found that compressive stress on the SiO2/Si interfacial region reduces both positive charge build-up and interface-trap generation. The positive charge build-up exhibits a smaller stress effect, as compared with the interface-trap generation. The magnitude of stress effect depends only on the compressive strength, and not on the silicide material, if the annealing conditions are the same. In addition, as the gate-oxide thickness decreases, the stress effect on positive charge build-up increases, while the interface-trap generation remains nearly constant. These results can be explained on the basis of the bond reformation process, i. e., in a region where compressive stress exists, the broken bonds are reformed with high probability. Futhermore, radiation response of MOS transistors with different gate-oxide stress values have been evaluated, and compared with those observed in MOS capacitors. Similar stress effects were also obtained.

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.

Threshold voltage of a narrow-width MOSFET

A simple closed-form analytical expression of the threshold voltage for a narrow-width MOSFET is developed. The narrow-width model gives a threshold voltage expression as a function of gate oxide thickness, channel doping concentration, backgate bias and channel width. The theory is compared with experimental results and the agreement is close.