Fully-differential Amplifier Research Articles

Scalable, low-power and high-performance active-RC complex band-pass/low-pass filter with automatic frequency tuning applied to the Internet of Things

This article introduces a comprehensive 3rd Chebyshev active-RC complex band-pass/low-pass filter with an automatic cut-off frequency tuning circuit. The designed filter achieves 2 dB step gain control within the range of −6 dB–24 dB and 4 different bandwidth modes including low-pass modes and complex band-pass modes. A compact fully-differential (FD) amplifier with feedforward compensation and reverse pole splitting technique is used to meet the stringent filter's performance. The novel amplifier achieves an open loop gain of 62 dB and a maximum unity-gain bandwidth (UGB) of 732 MHz with VDD = 0.9 V and 0.32 mW of power dissipation. Using the proposed amplifier, the filter achieves the lowest power consumption reported in the literature for active-RC implementations and 30 % power reduction over similar active-RC filters. By employing an optimized solution for dynamic allocation of inter-stage gain, the filter achieves a maximum in-band-IIP3 of +25.7 dBm and an improvement of 2 dB. Also, an automatic frequency tuning scheme is used to eliminate the effect of process variation. The filter is fabricated in 22 nm CMOS process occupying 0.44 mm × 0.44 mm area and consuming 1.8 mW and 1.2 mW from 0.9 V supply voltage in Wi-Fi and BLE modes, respectively. The maximum figure of merit (FoM) is 142.6 dB/J. The RC tuning circuit has a precision of 1.5 % and covers a range of 20 %.

A novel-16–60 V input common-mode voltage current-shunt monitor

This paper presents an effective design solution for current-shunt monitor (CSM) adapting to both positive and negative power supply applications, where the supply voltage is input common-mode voltage (CMV) of CSM ranged from −16 to 60 V. The proposed CSM mainly consists of a high-voltage low-drop output (HVLDO) regulator, a CSM core, and a 2nd-stage gain generator. The HVLDO regulator converts the independent supply voltage (5-16 V) to a stable internal output supply voltage of 5 V for other consequent circuits. The proposed CSM core adopts a fully-differential amplifier, a single-ended output amplifier, current-mirror transistors, and several resistors to constitute a stable negative feedback system. Due to its stable operation, the CSM core with both positive and negative CMV can successfully detect drops across the shunt resistor. The 2nd-stage generator is used to achieve a higher gain. By selecting proper transistor and resistor size in both CSM core and 2nd-stage gain generator, a total scaled gain of 100 V/V is achieved in this study. The proposed CSM architecture has been successfully implemented in a 0.25μm Bipolar-CMOS-DMOS (BCD) technology, and the area is around 1.44 mm2. Measurements show that the proposed CSM with an input CM voltage ranged from -16–60 V can sense an input voltage difference 4–16 mV.

Offset-free DC-coupled analog frontend circuit for high-dynamic-range signals

The analog frontend (AFE) coupling circuit is a crucial processing element for data acquisition systems based on analog-to-digital converters (ADCs). Currently, high-speed and high-resolution ADCs are predominantly designed with differential input stages. Conventional high-speed ADC drivers are mainly AC-coupled by employing transformers (Baluns) or fully differential amplifiers (FDAs) with blocking capacitors. However, the results of this study indicate that a certain degree of DC offset error exists and manifests itself as the baseline error in the presence of power dividers connecting several DC-coupled channels that implement high-dynamic-range (HDR) signal conditioning. The study involves a theoretical analysis and explanation of the baseline offset error. The offset error can potentially lead to unexpected out-of-range issues for sampling devices, including high-speed ADCs and switched capacitor array ASICs. High-performance FDAs are adopted, and an offset-free DC-coupled AFE circuit is proposed to address the aforementioned issue using two-stage amplification and a resistive attenuator. The proposed methodology is verified via circuit simulations and hardware design. Thus, the baseline offset problem can be accurately solved using the proposed circuit by minimizing the neglectable error. The proposed circuit facilitates improvements in the high-precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC-coupling scheme with FDAs involving resistive power dividers.

A 0.6V, 8.4uW AFE circuit for biomedical signal recording

For the detection of biomedical signal in wearable health devices, in this paper a fully-integrated, low-power, low-noise analog front-end (AFE) circuit is proposed. The AFE circuit includes a fully-differential amplifier with high-pass characteristics and a 14bit/500 Hz Sigma-Delta modulator based on cascode inverter. The fully-differential amplifier increases the output swing and improves the signal to noise ratio (SNR). Inverter-based Sigma-Delta modulator using bootstrapped switch completes high accuracy signal sampling in low supply voltage and finally outputs digital code. Two subthreshold bandgaps provide stable bias current and reference voltage for amplifier and Sigma-Delta modulator respectively. The circuit is fabricated with SMIC 0.13 μm CMOS mixed-signal technology occupying area of 1.68 mm2. The measurement results show that when the power supply voltage is 0.6 V, the input referred voltage noise of amplifier is 3.976μVrms and noise efficient factor (NEF) is 3.658. The maximum signal to noise and distortion ratio (SNDR) of AFE is 66.7 dB with only 8.4μw power consumption. Compared with the previous references, it has the maximum SNDR among them.

Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques

Existing yield analysis methods are computationally expensive and generally encounter challenges with high-dimensional process parameters space. In this paper, we propose a new method for accelerated and reliable computation of parametric yield that combines the advantages of sparse regression and satisfiability modulo theory (SMT) solving techniques, and avoids issues in both. The key idea is to characterize the failure regions as a collection of hyperrectangles in the parameters space. Toward this goal, the method constructs sparse polynomial models based on adaptive least absolute shrinkage and selection operator to find low degree approximations of the circuit performances. A procedure inspired by statistical model checking is then introduced to assess the model accuracy. Given the constructed models, an SMT-based solving algorithm is employed to locate the failure hyperrectangles in the parameters space. The yield estimation is based on a geometric calculation of probabilistic volumes subtended by the located hyperrectangles. We demonstrate the effectiveness of our method using circuits that require expensive run-time simulation during yield evaluation. They include: an integrated ring oscillator, a 6T static RAM cell and a multistage fully-differential amplifier. Experimental results show that the proposed method is suitable for handling problems with tens of process parameters. Meanwhile, it can provide $5{\times }{-}2000{\times}$ speed-up over Monte Carlo methods, when a high prediction accuracy is required.

Silicon Carbide Fully Differential Amplifier Characterized Up to 500 °C

This paper presents a monolithic fully differential amplifier implemented in a low-voltage 4H-silicon carbide bipolar junction transistor technology. The circuit has been designed, considering the variation of device parameters over a large temperature range. A base-current compensation technique has been applied to overcome the low input resistance of the amplifier. The bare chip of the amplifier has been measured from 27 °C to 500 °C using a hot-chuck probe station. Its open-loop gain is 58 dB at 27 °C, and monotonically decreases to 37 dB at 500 °C. Its closed-loop gain reduction is $\sim 5$ dB over the investigated temperature range. The gain-bandwidth product drops from 2.8 MHz at 27 °C to 1.3 MHz at 500 °C with 470 pF off-chip compensation capacitors. A low total-harmonic-distortion of −58.4 dB at 27 °C and −46.9 dB at 500 °C is achieved due to the fully differential implementation. A low input offset voltage of 0.5 mV at 27 °C and 6.9 mV at 500 °C is achieved without calibration. The relative high linearity and the low offset demonstrate the potential of this technology to be further investigated for the front-end sensor circuits in high-temperature applications.

Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis

This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits.

Design of CMOS Differential Transimpedance Amplifier

This paper explores the design of a differential transimpedance amplifier (TIA) integrated circuit for use in optical time domain reflectometer (OTDR) optical receivers (OR). All dependences between primary TIA design variables including OTDR laser pulse width, OR bandwidth, and TIA feedback resistance, are defined. Then, based on these dependencies, it is shown analytically that to achieve a stable system with no overshoots, the open-loop bandwidth of the fully differential amplifier (FDA) at the core of the TIA must exceed closed-loop TIA bandwidth by a factor of at least four. According to equations that are provided, it is shown that minimum amplifier noise occurs when detector and input transistor parasitic capacitances are equal. Schematics and short descriptions of all important TIA components, including the FDA and beta multiplier-based bias circuits, are given. The FDA has a bandwidth of 900 MHz. With a feedback resistance value of 20 kΩ the TIA has a closed-loop bandwidth of 125 MHz. TIA power consumption does not exceed 15 mW and at low bandwidths a variable feedback resistance allows the FDA to achieve up to 7 dB higher dynamic range. The area of the TIA integrated circuit is 100 µm × 250 µm excluding contact pads.DOI: http://dx.doi.org/10.5755/j01.eee.21.1.4548

An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing

<?Pub Dtl=""?> We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channel's differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{n}$</tex></formula> ) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 µV <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$_{rms}$</tex></formula> and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifier's four channels yields an effective NEF of 1.64. The total power consumption is 15.6 µW, or 3.9 µW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex> </formula> . The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers.

Pathological Equivalents of Fully-Differential Active Devices for Symbolic Nodal Analysis

The use of pathological elements (i.e., nullators, norators, and the voltage mirror-current mirror pair) as universal active elements opens up the possibility to model the behavior of active devices with either differential features or input-output multiples, in order to be used in analysis tasks of linear(ized) analog circuits. This brief tries on the modeling this class of active devices, which is carried out by considering the impedance characteristics along with the behavior equation of each active device, the kind of signal to be processed and by applying the pathological element properties. In order to obtain a more realistic model, not only parasitic elements associated to the input-output terminals of each active device are considered, but the tracking errors of voltage and current differential followers modeled with grounded pathological elements and admittances are also included. Due to that the gain and tracking errors are finites and of limited bandwidth, a two-pole model is used for each of them in order to include their contributions on the symbolic expressions computed. Because the behavior of fully-differential amplifiers is modeled with grounded pathological elements, a standard nodal analysis can be performed. This imply that not only the size of the admittance matrix is smaller than those generated by applying modified nodal analysis (MNA) method, for instance, but also the number of nonzero elements and the generation of cancellation-terms are both reduced. As a result, the computational complexity during the solution of the system of equations is reduced when recursive determinant-expansion techniques are applied. Examples are described and compared with the MNA method, in order to show the usefulness of the proposed models to compute fully-symbolic small-signal characteristics of analog circuits containing fully-differential active devices and/or with input-output multiples.

A 75dB Programmable Gain Amplifier for Dual Mode Wireless Receivers

In this paper, a programmable gain amplifier (PGA) is designed and implemented for GPS/Galileo and WCDMA dual mode receiver using TSMC 0.18μm CMOS technology. The 0-75dB variable gain range is obtained by cascading a 0-15dB variable gain stage and four 15dB fixed gain stages. An open-loop structured fully-differential amplifier with source feedback resistor is adopted in basic gain stage. Variation of gain is achieved by switch-controlled output resistor network. Gm-boost structure is used in main amplifier. A DC-offset canceller circuit using DC negative feedback technique is proposed to eliminate the DC-offset of the PGA. Post-simulation shows that the PGA has 0-75dB variable gain range, 1dB gain resolution and less than 0.3dB gain error; the minimum DC attenuation is about 15dB over the whole gain range; -3dB bandwidth at the maximum gain configuration is about 15MHz; differential output peak to peak voltage is greater than 1V; and the entire circuit consumes about 3.6mA current under 1.8V supply voltage.

A 0.5-V 35-$ \mu $W 85-dB DR Double-Sampled $\Delta\Sigma$ Modulator for Audio Applications

This paper presents a 0.5-V 1.5-bit double-sampled ΔΣ modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled ΔΣ modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-μm CMOS technology with a core area of 0.57 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured results show that when operating from a 0.5-V supply and clocked at 1.25 MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2 μW for a 20-kHz signal bandwidth.

A 0.6-V 82-dB 28.6-$\mu$W Continuous-Time Audio Delta-Sigma Modulator

The design of a low-voltage low-power fourth-order single-bit continuous-time Delta-Sigma modulator is presented in this paper for audio applications. The modulator employs an input-feedforward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers leading to low-voltage operation and low-power consumption. The energy efficiency is further improved by embedding the summation of feedforward paths into the quantizer. For low-voltage operation, a gain-enhanced fully-differential amplifier and a body-driven rail-to-rail input CMFB circuit are developed. The modulator, implemented in a 0.13-μm standard CMOS technology with a core area of 0.11 mm2, achieves an 82-dB dynamic range (DR), and a 79.1-dB peak signal-to-noise and distortion ratio (SNDR) over a 20-kHz signal bandwidth. The power consumption of the modulator is 28.6 μW under a 0.6-V supply voltage. The achieved performance make it one of the best among state-of-the-art sub-1-V modulators in terms of two widely used figures of merit.

A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta–sigma modulator

A 0.5-V high performance continuous-time one-bit delta---sigma modulator is reported for audio applications. High performance under this ultra-low supply is achieved by a feed-forward modulator architecture for reduced integrator swing, a special switched-capacitor-resistor feedback for less sensitivity to jitter noise, and a fast-settling fully differential amplifier. The synthesized modulator also has a high thermal-noise-limited SNR of 91 dB over a 20 kHz bandwidth. The 0.5-V fully-differential gate-input amplifier employs an adaptive common-mode feedback frequency compensation circuit, which leads to a robust modulator performance against process, supply voltage and temperature variations. Fabricated in a standard 0.13 μm CMOS process, the modulator achieves a spurious-free dynamic range (SFDR) of 101.9 dB and a signal-to-noise plus distortion ratio (SNDR) of 90 dB (A-weighted) over a 20-kHz signal bandwidth, with the latter being very close to the thermal noise limit. The modulator operates over a supply range from 0.4 to 0.75 V and a temperature range from ?20 to 90°C.

DESIGN OF AN INTEGRATED SCANNING MICROMIRROR DRIVER IN BCD TECHNOLOGY

The paper presents the design and characterization of a smart IC driver for MEMS scanning micromirrors. The driver integrates in 0.18 μm BCD technology the cascade of the following circuits: resistor-string DAC circuitry for direct interface to a host digital processing unit, a voltage buffer between the DAC and the High-Voltage (HV) stage, and a fully-differential HV amplifier with programmable output common mode. A couple of the designed DACs permits to generate, starting from digital samples, low-voltage analog stimuli. This signal amplified up to 25 V by the HV stage provides the electrostatical actuation of the micromirror. When compared to state-of-the-art the driver offers an integrated solution with good dynamic performances.

Design of High-SNR CMOS Interface Circuit for Micro-Machined Gyroscope

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.

Comparison of Quasi-/Pseudo-Floating Gate Techniques and Low-Voltage Applications

The quasi- or pseudo-floating gate (QFG) technique addresses a key issue with the floating-gate MOS transistor technique, by using ultra-high resistances to provide dc paths to otherwise floating nodes. Several ways have been suggested to implement the quasi-infinite resistors (QIRs). In this paper, basic QIR structures are analyzed and compared, and three sources of error, dc offset, signal distortion, and signal-dependent offset, are defined. Then, through simulations and experiments, the suitability of several QIR implementations for use in various applications is compared. A particular QIR implementation is found to minimize dc offset, but requires voltage swings to be limited to less than a diode turn-on voltage. Some application circuits using quasi-floating gate are presented, including a QFG translinear geometric-mean circuit and QFG low-voltage fully-differential amplifiers with QFG common-mode feedback using several QIR structures. Measurements on current-mode QFG circuits exhibit large offsets and very long turn-on transients, which could limit practical application of this technique.

A CMOS infrared wireless optical receiver front-end with a variable-gain fully-differential transimpedance amplifier

A CMOS infrared wireless optical receiver front-end is presented. A stable variable-gain fully-differential transimpedance feedback amplifier is designed employing a current-mode amplifier as the feedforward gain element. More than a triple variation of the transimpedance gain, from 0.3 k/spl Omega/ to 1 k/spl Omega/, the variable-gain transimpedance amplifier achieves desirable gain-bandwidth independence. For an infrared wireless optical receiver front-end employing the transimpedance amplifier, the optical preamplifier achieves a transimpedance gain of 66 dB/spl Omega/ and a bandwidth of 114 MHz with a 5 pF photodiode capacitance, and a power consumption of 17.4 mW.