Full Nyquist Band Research Articles

Recursive wideband digital differentiator and integrator

A new design of a recursive wideband digital differentiator is obtained by optimising the pole-zero locations of existing recursive wideband digital differentiators. Further, a new integrator design is also obtained by inverting the transfer function of the proposed digital differentiator design with suitable modifications. The beauty of these designs is that they are only of second-order recursive systems and have not more than 0.48% relative error in magnitude responses almost over the full Nyquist band, thus being suitable for real-time circuit applications.

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.

ADC compensation using a sinewave histogram method

The need for high dynamic range analog to digital converters (ADCs) is strong due to the growing use of digital signal processing in communications applications. ADC performance has improved over the years due to advances in both design concepts and semiconductor technologies. However most ADCs still still exhibit undesirable distortion in addition to quantization error, thus limiting spurious free dynamic range, (SFDR), in digital receiver applications. This paper describes a new method for developing ADC error function models using standard sinewave histogram methods. The method provides better error representation by providing error basis functions for every state. Results show this method is capable of removing all slope dependent errors in complex ADC error models and application to a 200 MSPS ADC showed more than 10 dB improvement in SFDR over the full Nyquist band for the ADC.

Using sine wave histograms to estimate analog-to-digital converter dynamic error functions

This paper describes a new method for developing analog-to-digital converter (ADC) error function models using modified sinewave histogram methods. The error models may be used to digitally compensate for nonlinearities introduced by the converter. The histogram modification involves sorting of converter output samples based upon an estimated associated input derivative signal. This error model is based upon a previously unpublished result which shows that sinewave histograms yield distinctly different expected errors for each state based upon input signal slope associated with each output sample. This result thus provides a dynamic dependence for expected errors measured by means of histogram methods. Sorted sinewave histograms are used to estimate slope dependent expected errors at each ADC output state (code). The method provides improved error representation by providing error basis functions for every output code. Simulated results prove that this method removes all slope dependent errors for complex ADC architectures while experimental results for an 8-bit 200 MSPS ADC yielded more than 10 dB improvement in spurious-free-dynamic-range (SFDR) over the full Nyquist band. The new method is thus shown to possess wideband dynamic error character.

A 1.2-GS/s 8-b silicon bipolar track & hold IC

An Si bipolar all-NPN track & hold (T&H) IC is presented for operation up to 2 GS/s. It is based on a switched emitter-follower design. The total harmonic distortion is less than -52.4 dB, corresponding to 8.4 b, up to 1.2 GS/s over the full Nyquist band. Fabricated in a 25 GHz f/sub T/ 0.4 /spl mu/m emitter width production technology, the IC consumes 460 mW, excluding the test buffer. The transistor count is 67. The T&H lends itself as a building block for multistage high-speed 8-b A/D-converters.

Fully bipolar, 120-Msample/s 10-b track-and-hold circuit

Describes the design and experimental results of a fully bipolar track-and-hold (T&H) circuit for use in video applications. A fully differential, open-loop approach has been chosen in order to meet the specifications with respect to track-to-hold step, droop rate, and hold-mode feedthrough. In order to obtain maximum high-frequency performance, p-n-p transistors have been omitted from the design. The T&H circuit has been realized in a 3-GHz f/sub T/ bipolar production process with a minimum emitter size of 2*9 mu m/sup 2/. The die size is 0.25 mm/sup 2/, consuming 40 mW from a single 5-V power supply. Ten-bit performance has been measured up to 12-Msample/s full-Nyquist sampling rate. At 200 Msample/2, 8-b performance has been observed over the full-Nyquist band.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>