Full Modulation Range Research Articles

A Double Vector Model Predictive Torque Control Method Based on Geometrical Solution for SPMSM Drive in Full Modulation Range

A Double Vector Model Predictive Torque Control Method Based on Geometrical Solution for SPMSM Drive in Full Modulation Range

A Fault-Tolerant Inverter Circuit to Generate Thirteen-Level 24-Sided Voltage Space Vector Structure for Open-End Winding Induction Motor Drive

An inverter circuit to generate a 13-level 24-sided polygonal voltage space vector structure (VSVS) comprised of 288 real active vectors and a zero vector is proposed in this article. The proposed scheme eliminates lower order harmonics up to 19th order and suppresses higher order harmonics from motor phase voltage in the full modulation range. The 48-step operation of the proposed scheme highly improves phase voltage quality at full speed. The dc bus utilization of the proposed scheme is improved to 99.42% compared to 90.6% multilevel hexagonal VSVS. The proposed topology has inherent capacitor balancing in every sampling interval at any loading condition using pole voltage redundancies. Multilevel property of the proposed scheme reduces instantaneous error in phase voltage compared to two-level 24-sided polygonal VSVS. Generation of real active vectors reduces instantaneous error in phase voltage and reduces switching frequency compared to switched average techniques existing in the literature. Fault-tolerant feature of the proposed scheme improves the availability of the drive system. Experimental results are provided to validate the steady-state operation, capacitor balancing, transient performance, and fault-tolerant capability of the proposed scheme. The comparison of switching loss and harmonic performance of the proposed scheme is performed with existing topologies.

A General Multilevel Polygonal Space Vector Generation Scheme With Reduced Switching for the Inverter and Harmonic Suppression Using a Switched-Capacitive Filter for the Full Modulation Range

In this article, a general multilevel polygonal space vector generation scheme is proposed for open-end induction motor drive schemes, fed with any conventional multilevel inverter with active dc-link supply on one end and a low-voltage capacitor-fed inverter working as a switched-capacitive filter on the other end. The main power delivery primary inverter provides active power for motoring operation, and the capacitor-fed secondary switched-capacitive filter suppresses lower order harmonics by forming polygonal space vector structures of 36, 42, 48, etc., sides. In the proposed general modulation scheme, the primary inverter is visualized as a combination of subhexagons. Two subhexagons of the primary inverter are modulated in the pseudo six-step mode of operation to generate the desired fundamental component to drive the induction motor load. The primary inverter also generates undesirable lower order harmonics due to low switching per cycle in the primary inverter. The secondary inverter is used as a switched-capacitive filter to suppress the lower order harmonics of the 5th, 7th, 11th, 13th, etc., order by forming polygonal switching vectors with sides more than six, i.e., 36, 42, 48, etc. The proposed general scheme is verified for a three-level primary inverter fed with an active dc link of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V_{\text{dc}}$</tex-math></inline-formula> and a six-level secondary inverter fed with a capacitive supply balanced at nearly one-third of the dc-link voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{0.39}V_{\text{dc}}$</tex-math></inline-formula> ).

Strategy of Synchronized SVPWM for Dual Three-Phase Machines in Full Modulation Range

In high-power drives, the switching frequency of the inverter is always strictly limited to avoid high switching losses. Synchronized space vector pulsewidth modulation (synchronized SVPWM) is usually adopted in this case to reduce harmonic distortion. In this article, an effective synchronous modulation strategy based on 24-sector SVPWM is proposed for dual three-phase machines in the full modulation range. A more accurate criterion is proposed to select the implementation under different pulse patterns through the inductance characteristics analysis of the dual three-phase machines. A new overmodulation strategy considering harmonics performance is proposed to guarantee a smooth transition to square wave mode under each pulse pattern. Besides, more pulse patterns are created in this article that satisfy voltage symmetry conditions, and it can reduce the sudden drop in switching frequency to improve control performance during the pulse pattern change. The proposed synchronized SVPWM strategy and its implementation method are validly verified by simulation and experimental results in the field-oriented-control system.

Suppression of Lower Order Harmonics for the Full Modulation Range for a Two-Level Inverter-Fed IM Drive With a Switched-Capacitive Filter Technique Forming a 42-Sided Voltage Space Vector Structure

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme.

Vector Control of Asymmetric Dual Three-Phase PMSM in Full Modulation Range

The total control range of asymmetric dual three-phase permanent magnet synchronous motor (ADT_PMSM) is divided into three different segments by voltage modulation range and current control dimensions and respective control strategies to get the injected voltages in harmonic subspace for three segments are presented in this paper. The three segments are sinusoidal current modulation region, sinusoidal voltage modulation region and overmodulation region. In sinusoidal current modulation region, resonant controller is adopted in the harmonic subspace to calculate the injected voltages, which can compensate the effect of six-phase voltage source inverter (VSI) dead time for two sets of three-phase windings and takes the pole correction into consideration. In sinusoidal voltage modulation region, open loop control strategy in harmonic subspace is adopted. Overmodulation region 1 and 2 are defined in overmodulation region, and the harmonic voltages which are injected into harmonic subspace to extend the modulation index are calculated based on superposition principle and VSD theory. In order to achieve smooth transition from different regions, a novel space vector pulse width modulation (SVPWM) technique for ADT_PMSM is proposed. The experimental results demonstrate the validity and feasibility of the suggested control approach.

Vector Weighting Approach and Vector Space Decoupling Transform in a Novel SVPWM Algorithm for Six-Phase Voltage Source Inverter

For six-phase permanent-magnet synchronous motor (PMSM) which has two sets of Y-connected three-phase windings spatially phase shifted by 30 electrical degrees, to increase the utilization ratio of the DC bus voltage, a novel space vector pulse width modulation (SVPWM) algorithm in full modulation range capability based on vector weighted method is proposed in this paper. The basic vector action time of SVPWM method is derived in detail, employing vector space decomposition transformation approach. Compared with the previous algorithm, this strategy is able to overcome the inherent shortcomings of the four-vector SVPWM, and it achieves smooth transitions from linear to overmodulation region. Simulation and experimental analyses demonstrate the effectiveness and feasibility of the proposed strategy.

Capacitor Voltage Balance Control of Five-Level Modular Composited Converter With Hybrid Space Vector Modulation

Multilevel converters are widely employed in the 30–50 kW medium-voltage grid-connected photovoltaic (PV) generation systems due to their higher power quality and lower switching losses compared with the two-level converters. Dual T-type three-level converters and one three-level diode neutral point clamped circuit can be integrated to derive a simplified five-level modular composited converter (5L-MCC) for the medium-voltage PV grid-connected systems. However, realizing the capacitor voltage balance is a challenge to enhance its reliability. First, the model of dc capacitor voltage variation of the 5L-MCC is discussed to expose a limitation once the nearest three-vector synthesis method is employed with conventional space vector modulation (SVM). In order to extend the operational range, a hybrid space vector modulation (HSVM) strategy is proposed, which integrates the optimized SVM switching sequence for the low-modulation ( $M\, ) and a simplified vector synthesis method for the high-modulation region ( $M\geq 0.5$ ). The proposed hybrid modulation maintains the dc capacitor voltage balance over the full modulation range and power factor. Finally, the effectiveness of the proposed HSVM strategy is verified with the simulation and experimental results.

A Harmonic Suppression Scheme for Full Speed Range of a Two-Level Inverter Fed Induction Motor Drive Using Switched Capacitive Filter

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth-and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth-and seventh-order harmonics for the full speed range.

Low Switch Count Nine-Level Inverter Topology for Open-End Induction Motor Drives

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included.

A Three-Level Dodecagonal Space Vector-Based Harmonic Suppression Scheme for Open-End Winding IM Drives With Single-DC Supply

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at $0.1445V_{\text{dc}}$ . The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds $\frac{2}{3}V_{\text{dc}}$ (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive.

Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method.

Low-Order Harmonic Suppression for Open-End Winding IM With Dodecagonal Space Vector Using a Single DC-Link Supply

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique.

A Five-Level Inverter Topology with Single-DC Supply by Cascading a Flying Capacitor Inverter and an H-Bridge

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.

A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using Two-Level Inverters in Series With a Capacitor-Fed H-Bridge Cell

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulation range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drive system. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

A Novel Split Phase Induction Motor Drive without Harmonic Filters and with Linear Voltage Control for the Full Modulation Range

A modulation scheme for a split phase (six phase) induction motor is presented in this paper. For a six phase induction motor drive harmonics of the order 6n ± 1 (n = 1, 3, 5 etc.,) will not contribute to the air gap flux and hence these harmonic currents are limited by the stator impedance only. So harmonic filters are needed for the suppression of these (6n ±1( n = 1, 3, 5 etc.,) high amplitude harmonic currents, when a six phase induction motor is used for variable speed application. In the proposed scheme, a modulation technique to eliminate the 6n ± 1 (n = 1, 3, 5 etc.,) harmonic currents, without the need for harmonic filters, from the stator phases of a six phase induction motor drive is explained. An openend winding drive configuration with appropriate DC-link voltages, is chosen in such away that a 12-sided polygonal voltage space phasor combinations are achieved for each 3-phase group, independently. A modulation scheme based on 12-sided polygonal voltage space phasors cancel the 6n ± 1 (n = 1, 3, 5 etc.,) harmonic voltages from all the motor phases and hence currents due to these harmonics can not flow in the motor phases of the six phase machine. For the same flux level of operation, nearly 11.5 % increase in modulation range is possible from this proposed drive (while still being in the linear PWM range), which is more than that of a six-step over modulation region in a conventional 3-phase induction motor drive. The proposed drive scheme is experimentally verified, for variable speed application, using a 1.5 kW six-phase induction motor drive.