Full-custom IC Design Research Articles

Design of basic CMOS cell library

The paper was developed from an undergraduate student project carried out in 1989. The aims were to investigate the principles behind cell library design, and then to design a rudimentary cell library for use in connection with full-custom IC design teaching and projects. The library itself was targeted at the ES2 2 μm n-well process, and was built using the RACAL-REDAC ‘ISIS’ full-custom software suite, but the principles discussed should be of more general interest. The paper considers the general options available, the sequence of design decisions that need to be taken, and factors that may influence these decisions. Some unexpected and unresolved difficulties with simulators and simulation are reported, and some general conclusions about designing a cell library are noted.

Development of a Dolby S-type IC using a new master slice method

A novel IC has been developed to implement the Dolby S-type noise reduction process. The IC was developed using a novel bipolar master slice (M/S) process. This method has several advantages over full custom IC design, including lower cost, fast turn around time, more design flexibility, and quick assessment and correction of design problems. The advantages of the new M/S method were particularly useful in the design of the S-type IC. This is because the system design changed to accommodate integration and performance requirements, and SPICE evaluation was difficult. The resulting IC is a very-high-performance, low-cost, single package which should find good acceptance among manufacturers and consumers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Recent developments and trends in bipolar analog arrays

Recent developments in bipolar analog arrays are reviewed. The use of tiles, their characteristics, and impact on design is evaluated. The progression from breadboarding to computer-aided simulation of array circuits with sophisticated transistor models is discussed. Design layout tools and functional libraries for the user are also reviewed in terms of their importance to analog array design. The increased use of arrays has revealed new problems and responses to them are discussed. Limitations of analog arrays with respect to full custom IC design are delineated. The paper concludes with a short discussion of future trends.