Front-end Prototype Research Articles

PERANCANGAN USER INTERFACE DAN USER EXPERIENCE APLIKASI BERBASIS WEB UNTUK KLINIK TERAPI MENGGUNAKAN METODE USER CENTERED DESIGN (STUDI KASUS: KLINIK RUMAH TERAPI SAHABAT)

Rumah Terapi Sahabat Clinic is located in West Pagesangan, West Nusa Tenggara and has been around for seven years since it was founded in 2015. Based on the results of observations, Focus Group Discussions and interviews, this clinic needs a way to digitize clinical data storage so that it can be accessed easily by clinic staff. In order to meet these needs, a website-based application for clinics is needed with patient and therapist data storage features as well as therapy scheduling. To be able to realize this application, User Interface and User Experience are needed. The method used to do this is User Centered Design. After creating a good User Interface, testing will be carried out using the System Usability Scale and User Experience Questionnaire methods to find out how functional and experienced the clinical staff are while using this Front-end prototype and aspects that can be improved in the future. This research will have results in the form of a front end of a website-based application that suits the needs of clinic staff. While testing using SUS and UEQ, the end result of SUS is 84 or “Acceptable” meanwhile five out of six categories from UEQ are graded “Excellent”

Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a 5 × 5-pad matrix and contains the analog part of the single-channel readout (preamplifier, discriminator, two TDCs and SRAM). Two preamplifier architectures (transimpedance and voltage) were implemented and tested. The ASIC was characterised both alone and as a module when connected to a 5 × 5-pad array of LGAD sensors. In calibration measurements, the ASIC operating alone was found to satisfy the technical requirements for the project, with similar performances for both preamplifier types. In particular, the jitter was found to be 15 ± 1 ps (35 ± 1 ps) for an injected charge of 10 fC (4 fC). A degradation in performance was observed when the ASIC was connected to the LGAD array. This is attributed to digital couplings at the entrance of the preamplifiers. When the ASIC is connected to the LGAD array, the lowest detectable charge increased from 1.5 fC to 3.4 fC. As a consequence, the jitter increased for an injected charge of 4 fC. Despite this increase, ALTIROC1 still satisfies the maximum jitter specification (below 65 ps) for the HGTD project. This coupling issue also affects the time over threshold measurements and the time-walk correction can only be performed with transimpedance preamplifiers. Beam test measurements with a pion beam at CERN were also undertaken to evaluate the performance of the module. The best time resolution obtained using only ALTIROC TDC data was 46.3 ± 0.7 ps for a restricted time of arrival range where the coupling issue is minimized. The residual time-walk contribution is equal to 23 ps and is the dominant electronic noise contribution to the time resolution at 15 fC.

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

Study on an abnormal temperature detection method for CAFe facility

Beam availability is an important indicator of the operational stability and safety of the accelerator. As the front-end prototype of CiADS (China initiative Accelerator Driven System), the CAFe (Chinese ADS Front-end Demo Linac) accelerator is used to verify the feasibility of the key technologies of CiADS, which plays an important role in the development of nuclear waste safety treatment technology. The accelerator is often affected by uncontrollable factors during operation, triggering false temperature alarms from the BPM (Beam Position Monitor), causing the accelerator machine protection system to cut the beam, significantly reducing the availability of the beam. In addition, the prevailing method of manually setting the machine protection system threshold increases the beam conditioning time and the probability of false beam cuts. Therefore, it is urgent to study and discriminate the anomalies that cause beam cutting in order to reduce the beam cutting times caused by false alarms. In this paper, a BPM temperature anomaly prediction model based on Isolation Forest is developed, and the historical BPM temperature data from the CAFe accelerator is pre-processed using the Kalman filter to eliminate the influence of noise. The experimental results show that the scheme can accurately predict the abnormal state of the accelerator to remove the anomalous values, thereby avoiding false interlocks, and provide an effective interlock reference for the threshold setting of the machine protection system, thereby improving the beam availability.

Advanced laser development and plasma-physics studies on the multiterawatt laser.

The multiterawatt (MTW) laser, built initially as the prototype front end for a petawatt laser system, is a 1053 nm hybrid system with gain from optical parametric chirped-pulse amplification (OPCPA) and Nd:glass. Compressors and target chambers were added, making MTW a complete laser facility (output energy up to 120 J, pulse duration from 20 fs to 2.8 ns) for studying high-energy-density physics and developing short-pulse laser technologies and target diagnostics. Further extensions of the laser support ultrahigh-intensity laser development of an all-OPCPA system and a Raman plasma amplifier. A short summary of the variety of scientific experiments conducted on MTW is also presented.

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 μW and 10.4 μW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 × 16 pixel matrix.

A high speed frontend electronics ASIC for multi-channel single gap RPC detector

This paper presents a high speed prototype frontend electronics (FEE) ASIC, designed to meet the readout requirements of ∼ 3.6 million channels of avalanche mode single-gap resistive plate chamber detectors of Iron Calorimeter experiment of India based Neutrino Observatory. This ASIC is a regulated cascode transimpedance pre-amplifier based octal amplifier-comparator FEE solution in 0.35 μm CMOS process. Two DC stabilization techniques, one for common mode and another for differential DC offset cancellation, have been incorporated in this ASIC to ensure amplifier baseline stability, uniform dynamic range and comparator overdrive across readout channels. This DC common mode control can also be used to trim the input impedance of regulated cascode pre-amplifier. The ASIC provides parallel LVDS outputs on external 100 Ω load for tracking and precision time-tagging. A multiplexed analog output is also provided through an on-chip 50 Ω cable driver for detector pulse profile analysis. The ASIC has total channel gain of ∼ 0.75 mV/fC for single ended inputs of both the polarities, intrinsic timing precision of ∼ 190 ps RMS and ∼ 100 ps RMS for input charge of 0.1 pC and beyond 0.3 pC respectively with total power consumption of 40 mW/channel.

Design, characterisation, and digital linearisation of an ADC analogue front-end for gamma spectroscopy measurements

&lt;p class="Abstract"&gt;This work presents the design, experimental characterisation, and digital post-distortion (i.e., digital linearisation) of a MHz-range ADC analogue front-end prototype for a gamma radiation spectrometry system under development at the National Center for Nuclear Research (NCBJ) in Poland. The design accounts for the electrical response of the gamma particle detector in providing signal conditioning and ADC protection against high-voltage spikes due to occasional high-energy cosmic radiation, as well as proper ADC clocking. As the front-end inevitably introduces nonlinear distortion and dynamic effects, a characterisation is performed to quantify the actual performance in terms of Total Harmonic Distortion (THD) and Effective Number of Bits (ENOB). Thus, a digital linearisation based on both static and memory polynomial models is successfully applied by means of post-distortion processing, guaranteeing a substantial improvement in THD and ENOB, and demonstrating the effectiveness of the hardware/software method for gamma radiation spectrometers. &lt;/p&gt;

A Passive-Mixer-First Acoustic-Filtering Superheterodyne RF Front-End

This article presents an agile passive-mixer-first superheterodyne RF front-end that utilizes a gigahertz acoustic filter as its intermediate-frequency (IF) load—essentially a mixer-first acoustic-filtering RF front-end . The passive mixer frequency-translates a sharp but fixed-frequency acoustic-filtering response to a much higher and mixer-clock-defined tunable frequency while preserves input matching, high linearity, and introduces minimal loss. In contrast to low- or zero-IF passive-mixer-first receivers which often use active filters at baseband, using an acoustic filter as the IF load is fraught with fundamental challenges. We introduce ON-chip LC tanks, as an impedance shaper , to suppress the acoustic filter impedance components at harmonic frequencies and an all-passive recombination network at IF to share one acoustic filter among multiple paths. Also, we extend the existing analysis of mixer-first front-ends from assuming a load impedance with a low-pass frequency response to having a generic load impedance. Our analysis unveils impedance aliasing in a generic mixer-first front-end, motivating the need for an ON-chip impedance shaper. A front-end prototype using a 65-nm CMOS switched- LC passive mixer followed by an off-the-shelf 1.6-GHz surface-acoustic-wave (SAW) filter is designed. In measurement, the RF front-end operates across 2.5-to-4.5 GHz achieving 5.5-dB noise figure and +29.4-dBm IIP3 at 1 $\times $ bandwidth offset.

An Ultralow-Power Current-Reused Direct-Conversion Bluetooth-Low-Energy Receiver Front-End in 40-nm CMOS

An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of -95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at -19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of -119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6- μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design Space Optimization of a Three-Phase LCL Filter for Electric Vehicle Ultra-Fast Battery Charging

State-of-the-art ultra-fast battery chargers for electric vehicles simultaneously require high efficiency and high power density, leading to a challenging power converter design. In particular, the grid-side filter, which ensures sinusoidal current absorption with low pulse-width modulation (PWM) harmonic content, can be a major contributor to the overall converter size and losses. Therefore, this paper proposes a complete analysis, design and optimization procedure of a three-phase LCL filter for a modular DC fast charger. First, an overview of the basic LCL filter modeling is provided and the most significant system transfer functions are identified. Then, the optimal ratio between grid-side and converter-side inductance is discussed, aiming for the maximum filtering performance. A novel design methodology, based on a graphical representation of the filter design space, is thus proposed. Specifically, several constraints on the LCL filtering elements are enforced, such that all feasible design parameter combinations are identified. Therefore, since in low-voltage high-power applications the inductive components typically dominate the overall filter volume, loss and cost, the viable LCL filter design that minimizes the total required inductance is selected. The proposed design procedure is applied to a 30 kW, 20 kHz 3-level unidirectional rectifier, employed in a modular DC fast charger. The performance of the selected optimal design, featuring equal grid-side and converter-side 175 μμH inductors and 15 μμF capacitors, is verified experimentally on an active front-end prototype, both in terms of harmonic attenuation capability and current control dynamics. A current total harmonic distortion (THD) of 1.2% is achieved at full load and all generated current harmonics comply with the applicable harmonic standard. Moreover, separate tests are performed with different values of grid inner impedance, verifying the converter control stability in various operating conditions and supporting the general validity of the proposed design methodology.

A 43–97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection

This article presents a wideband millimeter-wave (mmWave) receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E-, and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance. The front-end adopts I/Q generation at the RF port, using a coupled-line coupler (CLC), rather than at the local oscillator (LO) port to mitigate the crosstalk of the overlapping I/Q LO signals especially present at high frequencies. The CLC at the RF input facilitates ultrawide band input matching. The front-end implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer-based IF 90° coupler are implemented on chip and demonstrated with measurements. The front-end prototype is fabricated on the GlobalFoundries 22-nm FD-SOI CMOS process and it demonstrates an ultra-wideband performance across the frequency range 43-97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6-5.2 dBm, and gain of 15 dB. The implementation used is low-IF topology with 3.8-GHz IF frequency and 1-GHz bandwidth. Furthermore, the measurement results show that the front-end supports high-speed modulated signals of up to 6-Gbps 64QAM modulation data.

Thermal Analysis of a Skull Implant in Brain-Computer Interfaces.

The goal of this study is to estimate the thermal impact of a titanium skull unit (SU) implanted on the exterior aspect of the human skull. We envision this unit to house the front-end of a fully implantable electrocorticogram (ECoG)-based bi-directional (BD) brain-computer interface (BCI). Starting from the bio-heat transfer equation with physiologically and anatomically constrained tissue parameters, we used the finite element method (FEM) implemented in COMSOL to build a computational model of the SU's thermal impact. Based on our simulations, we predicted that the SU could consume up to 75 mW of power without raising the temperature of surrounding tissues above the safe limits (increase in temperature of 1°C). This power budget by far exceeds the power consumption of our front-end prototypes, suggesting that this design can sustain the SU's ability to record ECoG signals and deliver cortical stimulation. These predictions will be used to further refine the existing SU design and inform the design of future SU prototypes.

Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region, to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must exploit the large signal derivative and small noise provided by the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2×2 LGAD array of 1.1×1.1 mm2 pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC . The time walk effect, which arises from the different preamplifier response for various injected charges, can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.

Design of prototype Front-End Electronics for the Gamma-Gamma collider

The Gamma-Gamma collider is a scientific facility proposed in China to observe two unique interactions at the center-of-mass energy of 1–2 MeV, namely γγ scattering and electron-positron pairs. In the experiment, two γ beams generated by the Compton back-scattering of high-energy electron beams (∼200 MeV) and high-intensity laser beams will collide at the interaction point, and the products will be collected by CsI(Na) crystals and plastic scintillators, and then converted into electric signals by silicon photomultiplier (SiPM) detectors. In this paper, a prototype Front-End Electronics (FEE) is implemented to verify the design requirements concerning the noise level (no more than 3 mV), high sampling rate (1 GS/s) and low power consumption. The prototype FEE comprised 8 differential drivers, 2 low-power switch capacitor array (SCA) DRS4 chips, and an 8-channel Analog-to-Digital Converter (ADC). The input signals were first stored in DRS4 chips for time stretching, then digitized by the ADC, and finally sent to back-end electronics via an optical link. The noise (RMS) of each readout channel on the prototype FEE was less than 3 mV after offset correction, and the ENOB of the channels was better than 6.7 bit when the frequency of input sine waves was less than 70 MHz and the sampling rate of the DRS4 was 1 GS/s. Therefore, the performance of the prototype FEE meets the requirements of the Gamma-Gamma collider.

Multi-frequency point supported LLRF front-end for CiADS wide-bandwidth application

The China initiative Accelerator Driven System, CiADS, physics design adopts $162.5 \,\mathrm{MHz}$, $325 \,\mathrm{MHz}$, and $650 \,\mathrm{MHz}$ cavities, which are driven by the corresponding radio frequency (RF) power system, requiring frequency translation front-end for the RF station. For that application, a general-purpose design front-end prototype has been developed to evaluate the multi-frequency point supported design feasibility. The difficult parts to achieve the requirements of the general-purpose design are reasonable device selection and balanced design. With a carefully selected low-noise wide-band RF mixer and amplifier to balance the performance of multi-frequency supported down-conversion, specially designed local oscillator (LO) distribution net to increase isolation between adjacent channels, and external band-pass filter to realize expected up-conversion frequencies, high maintenance and modular front-end general-purpose design has been implemented. Results of standard parameters show an $R^2$ value of at least $99.991\%$ in the range of $-60 \sim 10\,\mathrm{dBm}$ for linearity, up to $18\,\mathrm{dBm}$ for P1dB, and up to $89\,\mathrm{dBc}$ for crosstalk between adjacent channels. The phase noise spectrum is lower than $80\,\mathrm{dBc}$ in the range of $0 \sim 1\,\mathrm{MHz}$, and cumulative phase noise is $0.006^\circ$; amplitude and phase stability are $0.022\%$ and $0.034^\circ$, respectively.

Comparator Offset Immune I/Q Calibration Technique for Direct Conversion Receiver

A comparator offset immune and area-efficient In-phase and Quadrature (I/Q) mismatch calibration technique is proposed for direct conversion receivers in the letter. Theoretical analysis is provided to explain the independence between comparator offset and error detection accuracy. For verifying the proposed method, a receiver front-end prototype, along with the proposed I/Q mismatch calibration, is designed and fabricated in the 0.18-μm technology. Experimental results show that Image Rejection Ratio (IRR) is 61.99 dB @15 MHz with a comparator offset ranging from 0 to 14 mV. And IRR for a wideband signal from 5 to 25 MHz is enhanced from 31.6 to 43.3 dB after calibration.

Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6 lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard $0.18~\mu \text{m}$ CMOS technology. It achieves transimpedance gain of 68.3dB $\Omega $ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of $0.97~\mu $ Arms. The chip occupies 0.78 mm2 while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC.

Performance of the Compact High Energy Camera SiPM Prototype Front-End Electronics proposed for the Cherenkov Telescope Array

The Compact High Energy Camera (CHEC) is a full-waveform capture camera, designed and proposed for the dual mirror, Schwarzschild–Couder, Small Sized Telescope of the Cherenkov Telescope Array. CHEC-S, the second prototype, is based upon silicon photomultiplier (SiPM) photodetectors optimised for single photon counting and nanosecond timing. The camera liquid-cooled focal plane plate comprises a total of 2048 SiPM pixels organised as 32 independent sensor and front-end electronics (FEE) modules providing event detection and signal digitisation of Cherenkov light flashes. Each module comprises an 8 × 8 tile of SiPM pixels, coupled to a 64-channel preamplifier-buffer followed by a FEE module based around the TARGET chipset, which combines triggering (T5TEA) and waveform capture (TARGET C) functionality.We describe a selection of end-to-end performance tests and results conducted at the University of Leicester in the UK. Testing was performed at single module level focusing on characterising the SiPM photodetectors, optimised preamplifier-buffer and updated CHEC-S FEE readout module. Presented results include single photoelectron response, gain-matching, signal range, electronic channel crosstalk, SiPM angular dependency and optical crosstalk.

Towards Gotthard-II: development of a silicon microstrip detector for the European X-ray Free-Electron Laser

Gotthard-II is a 1-D microstrip detector specifically developed for the European X-ray Free-Electron Laser. It will not only be used in energy dispersive experiments but also as a beam diagnostic tool with additional logic to generate veto signals for the other 2-D detectors. Gotthard-II makes use of a silicon microstrip sensor with a pitch of either 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to adaptive gain switching readout chips. Built-in analog-to-digital converters and digital memories will be implemented in the readout chip for a continuous conversion and storage of frames for all bunches in the bunch train. The performance of analogue front-end prototypes of Gotthard has been investigated in this work. The results in terms of noise, conversion gain, dynamic range, obtained by means of infrared laser and X-rays, will be shown. In particular, the effects of the strip-to-strip coupling are studied in detail and it is found that the reduction of the coupling effects is one of the key factors for the development of the analogue front-end of Gotthard-II.