Fraunhofer IMS Research Articles

Infrared Image Pre-Processing and IR/RGB Registration with FPGA Implementation

Infrared imaging sensors are frequently used in thermal signature detection applications in industrial, automotive, military and many other areas. However, advanced infrared detectors are generally associated with high costs and complexity. Infrared detectors usually necessitate a thermoelectric heater–cooler for temperature stabilization and various computationally complex preprocessing algorithms for fixed pattern noise (FPN) correction. In this paper, we leverage the benefits of uncooled focal plane arrays and describe a complete digital circuit design for Field Programmable Gate Array (FPGA)-based infrared image acquisition and pre-processing. The proposed design comprises temperature compensation, non-uniformity correction, defective pixel correction cores, spatial image transformation and registration with RGB images. When implemented on Xilinx Ultrascale+ FPGA, the system achieves a throughput of 30 frames per second using the Fraunhofer IMS Digital 17 μm QVGA-IRFPA with a microbolometer array size of 320 × 240 pixels and an RGB camera with a 1024 × 720 resolution. The maximum ratio of the standard deviation to the mean of 0.35% was achieved after FPN correction.

Fully Integrated Sensor Electronics for Inductive Proximity Switches Operating up to 250 °C

Abstract In this paper we present an integrated circuit for inductive proximity switches which requires very few external components and can operate under ambient temperatures up to 250 °C. The sensor system is realized in the Fraunhofer IMS H035 technology which was specifically developed for high temperature operation. The core of the circuit is built of an oscillator which is equipped with a peak detector and readout electronics for threshold detection, references and voltage regulators to provide the necessary internal voltages as well as extensive trimming capabilities to compensate for temperature effects. The circuit can be operated from a single dc-voltage supply from 12 to 35 Volts. Calibration data can be stored in an internal EEPROM. Switching distance and hysteresis are programmable for adapting the circuit to a wide range of different detector coils and sensor geometries. Two output signals are provided that can be independently set to function as push/pull or single ended switches with programmable polarity. The only external components required are blocking capacitors for supply voltage stabilization and the LC resonator circuitry. Reverse polarity protection and special high temperature ESD and clamping structures are also fully integrated on the silicon die.

Fabrication and electrochemical characterization of ruthenium nanoelectrodes

Abstract The Fraunhofer IMS has recently developed a technique for producing nanoelectrodes that are generated by atomic layer deposition (ALD) in a via deep reactive ion etching (DRIE) structured sacrificial layer. This method enables the fabrication of CMOS- and biocompatible nanoelectrodes with suitable ALD-materials. Improvements of the established fabrication processes and the electrochemical characterization of such electrodes are presented. In the frame of the Fraunhofer-Max-Planckcooperation project ZellMOS different types of nanoelectrodes are studied. Their diameter is in the range of 200 nm and thereby sufficiently small to be taken up by living cells. In addition, the electrodes are mechanically enforced by an oxide layer at the nanoelectrodes’ bottom.

High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology

Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper.

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology

Standard bulk CMOS technology targets operating temperatures of not more than 175°C. Silicon-on-insulator technologies are commonly used up to 250°C. In this work, we evaluate the limit for electronic circuit function realized in thin film SOI technologies for even higher temperatures. At Fraunhofer IMS, a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metallization with excellent reliability concerning electromigration, as well as voltage-independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of an NMOSFET transistor and a PMOSFET transistor are studied up to 450°C. In a second step, we investigate the functionality of a ring oscillator (representing a digital circuit) and a band gap reference as an example of a simple analog component. The frequency and the current consumption of the ring oscillator, as well as the output voltage and the current of the band gap reference, are characterized up to 450°C. We find that the ring oscillator still oscillates at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the band gap reference is in the specified range (change < 3%) up to 250°C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS technology to its real maximum temperature limits.

High Temperature Characterization up to 450 °C of MOSFETs and basic circuits realized in a Silicon-on-Insulator (SOI) CMOS-Technology

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. Silicon-on-Insulator-technologies are commonly used up to 250 °C. In this work we evaluate the limit for electronic circuit function realized in thin film SOI-technologies for even higher temperatures. At Fraunhofer IMS a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metalization with excellent reliability concerning electromigration, voltage independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of NMOSFET- and PMOSFET-transistors were studied up to 450 °C. In a second step we investigated the functionality of ring oscillators, representing digital circuits, and bandgap references as examples of simple analog components. The frequency and the current consumption of ring oscillators and the output voltage of bandgap references were also characterized up to 450 °C. We found that the ring oscillator still functions at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the bandgap reference is in the specified range up to 250 °C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS-technology to its real maximum temperature limits.

High Temperature Reliability Investigations of EEPROM Memory Cells Realised in Silicon-on-Insulator (SOI) Technology

Microelectronic manufacturing progresses not only towards further miniaturisation, but also application fields tend to become more and more diverse. Recently there has been an increasing demand for electronic devices and circuits that function in harsh environments such as high temperatures. Under these conditions, reliability aspects are highly critical and testing remains a great challenge. A versatile CMOS process based on 200 mm thin film Silicon-on-Insulator (SOI) wafers is in production at Fraunhofer IMS. It features three layers of tungsten metallisation for optimum electromigration reliability, voltage independent capacitors, high resistance resistors and single-poly-EEPROM cells. Non-volatile memories such as EEPROMs are a key technology that enables flexible data storage, for example of calibration and measurement information. The reliability of these devices is especially crucial in high temperature applications since charge loss is drastically increased in this case. The behaviour of single-poly-EEPROM cells, produced in the process described before, was evaluated up to 450 °C. Data retention tests at temperatures ranging from 160 °C to 450 °C and write/erase cycling tests up to 400 °C were performed. The dependence of write/erase cycling on both temperature and tunnel oxide thickness was studied. These data provide an important foundation to extend the application of high temperature electronics to its maximum limits. The results show that EEPROM cells can be used for special applications even at temperatures higher than 250 °C.

Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes

In this investigation we examine different pixel structures and readout principles to be used in imagers fabricated in standard CMOS processes, for example, the 0.5 and 0.35 processes available at the Fraunhofer IMS. The targeted applications are high-speed near-infra-red (NIR) 3-D imaging based on time-of-flight (TOF) measurements. We discuss various issues ranging from charge-coupling possibilities to noise, spectral responsivity and fill-factor, and present an extensive study of pixel configurations based on inverse biased p-n junction and MOS-C based photodetectors. We also discuss the possibilities of using a novel CMOS imaging pixel for TOF imaging applications: the charge-injection photogate (CI-PG) which presents parametric time-compression amplification. Finally, we compare and discuss all the pixel configurations examined.