FPGA TDC Research Articles

Plastic scintillator fiber detectors for heavy ion trajectory reconstruction for the Super-FRS at FAIR

At the FAIR facility, currently under construction at GSI (Darmstadt), a 1.5 AGeV uranium beam with intensities up to 2.5 × 1011 238U/spill will impinge on a graphite target at the entrance of the Super-FRS for the production of a wide range of rare isotopes by projectile fission and fragmentation. The next generation in-flight magnetic separator Super-FRS, operated up to a magnetic rigidity of 20 Tm with a large angular acceptance (Δθ = ± 40 mrad, Δϕ = ± 20 mrad) and momentum acceptance (Δ p/p = ± 2.5%), requires a new generation of tracking detectors with a position resolution of 0.2 mm (σx ) over large detector areas reaching up to 570 cm2. Besides gas detectors, planar detectors made of scintillating fibers are an option worth investigating not only because of the comparable material budget but especially for the fast response and high-rate capability. A one-dimensional prototype consisting of 128 fibers with active area of 25.6 × 100 mm2 coupled to Multi-Pixel-Photon Counters (MPPCs) and readout by FPGA TDC is described together with some recent 197Au beam test results.

Development of a 100 ps TDC based on a Kintex 7 FPGA for the high granular neutron time-of-flight detector for the BM@N experiment

The prototype of a TDC board has been developed for the new high granular time-of-flight neutron detector (HGND). The board is based on the standard LVDS 4x asynchronous oversampling using the xc7k160 FPGA with a 100 ps bin width. The HGND is being developed for the BM@N (Baryonic Matter at Nuclotron) experiment to identify neutrons and to measure their energies in heavy-ion collisions at ion beam energies up to 4 A GeV. The HGND consists of about 2000 scintillator detectors (cells) with a size of 40×40×25mm3 and light readout with EQR15 11-6060D-S photodetectors. To measure the time resolution of the scintillator cells, the two-channel FPGA TDC board prototype with two scintillator cells was tested with an electron beam of “Pakhra” synchrotron at the LPI institute (Moscow, Russia). The measured cell time resolution is 146 ps, which is in a good agreement with the 142 ps time resolution measured with a 12-bit @ 5 GS/s CAEN DT5742 digitizer. For the full HGND, the TDC readout board with three such FPGAs will read 250 channels. In total, eight such TDC boards will be used for the full HGND at the BM@N experiment.

Status and recent extensions of the Caribou DAQ system for picosecond timing with an FPGA TDC

Caribou is a flexible open-source DAQ system developed and used within several collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for laboratory and high-rate beam tests and easy integration of new silicon-pixel detector prototypes. It uses common hardware, firmware and software components that are shared across different projects, thereby reducing the development effort and cost for such readout systems significantly. This contribution introduces the FASTPIX, APTS and DPTS detectors recently integrated in Caribou and their requirements in terms of waveform sampling and timing of digital pulses. A Time-to-Digital-Converter implemented in the Caribou FPGA was developed to overcome the limitations of the previously used oscilloscope-based readout. It allows for precision timing over large time spans required for the Time-of-Arrival, Time-over-Threshold, and position encoding used in the FASTPIX and DPTS test chips with asynchronous digital readout. A time resolution after calibration of better than 10 ps is achieved.

Progress and perspectives of FARICH R&D for the Super Charm-Tau Factory project

Particle identification system based on Focusing Aerogel RICH (FARICH) detector is considered as an option for the future experiments at the Super Charm-Tau Factory (Russia). We present the progress of FARICH R&D at the Budker Institute of Nuclear Physics. New samples of focusing 4-layer aerogels with maximal refractive index 1.065 were produced in 2020–2021. First beam test results with relativistic electrons demonstrate single photon resolution (SPR) of 9÷10mrad. According to simulation results, the aerogels with such SPR are able to provide μ/π-separation at the level of more than 3 standard deviations for tracks with momentum 1.5 GeV/c. The first version of electronics to readout SiPM arrays based on TDC implemented on FPGA (FPGA-TDC) was developed and manufactured.

The integration of FPGA TDC inside White Rabbit node

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

A Stepped-Up Tree Encoder for the 10-ps Wave Union TDC

A stepped-up tree encoder (SUTE) has been designed to deal with the issue of non-thermometer-to-binary (NTH2B) encoding for a 10-ps wave union FPGA TDC. The encoder is made up of two pipeline stages: pre-encoding and parallel encoding, and is capable of bubble error correction (BEC) as well. With this encoding algorithm applied in a Xilinx Virtex-4 FPGA, we achieved a NTH2B conversion rate of up to 100 MHz for more than 200-bit non-thermometer codes.

A digitization scheme of sub-microampere current using a commercial comparator with hysteresis and FPGA-based wave union TDC

A digitization scheme of sub-microampere current using a commercial comparator with adjustable hysteresis and FPGA-based Wave Union TDC has been tested. The comparator plus a few passive components forms a current controlled oscillator and the input current is sent into the hysteresis control pin. The input current is converted into the transition times of the oscillations, which are digitized with a Wave Union TDC in FPGA and the variation of the transition times reflects the variation of the input current. Preliminary tests show that input charges < 25 fC can be measured at > 50 M samples/s without a preamplifier.

Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs

This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGA delay line based TDCs. FPGA specific issues such as considerations on the delay line choice in different FPGA families and encoding logic are first examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.