FPGA Synthesis Research Articles

Secure double MAC implementation for STBC based FECG monitoring

One of the best methods for assessing a baby’s health is foetal electrocardiography (FECG). Previously restricted to more widespread global disorders such as common ischemia, it is new way to investigating foetal heart rate irregularities. Current prenatal monitoring practices ignore critical FECG waveform elements that are the foundation of both pediatric, adult cardiac assessment, and instead of focusing solely on the foetal heart rate. In this paper we proposed Double Multiply-and-Accumulate (MAC) approach used for package operators into a single DSP block of commercial FPGAs, theoretically doubling the calculation speed for FECG monitoring. For a variety of technical reasons, they were using the Space-Time Block Code (STBC) monitoring mode of operation. To strengthen the security of FECG monitoring, the Advanced Encryption Standard (AES) method may be used with the double MAC operators using STBC based FECG monitoring that has been developed. The solution was then assessed using state-of-the-art the Space-Time Block Code (STBC) based FECG techniques, and its validity was confirmed using Verilog simulation and FPGA synthesis. The calculation throughput of an STBC-based FECG monitoring system was found to be doubled using the Double MAC approach. Our implementation result demonstrates that keys are necessary for 128-bit AES encoding and decoding operations via VHDL-coded transformations. It is now more vital than ever to do a feasibility analysis of any hardware design due to the increase in the number of ways presented for minimizing noise. The efficiency increased (92%), and the delay was decreased to 19.35 ns by employing this double MAC architecture. The simulation results demonstrate that transformations for coding on an FPGA are implemented using the Xilinx VIVADO tool.

Residue number systems with six modules and efficient circuits based on power-of-two diagonal modulus

The paper suggests an algorithm for finding Residue Number Systems (RNS) with six modules (6-tuples) with the Sum of Quotients SQ=2k for some positive integer k. It is shown that there are exactly thirteen such 6-tuples (m1,…,m6) with m1+m2≤10000 and m3+m4≤m5+m6≤10000 and investigated the three smallest among them, namely (5,2399,7,11,23,1691), (47,293,25,193,41,257), and (23,1433,13,29,681,821), having k=34, 36, and 40, respectively. The hypothesis is that such RNS allow efficient hardware implementations of non-modular operations — division, sign detection, comparison of numbers, and reverse conversion from the point of hardware resource usage and balancedness. The special case SQ=2k allows a significant simplification of these operations and increased efficiency of hardware implementations. Hardware modeling of circuits based on the above 6-tuples that implement magnitude comparison and reverse RNS to binary conversion (reverse conversion) is presented. The suggested magnitude comparison and reverse conversion devices, which operate with the six modules, are built using the methodology and values of the diagonal function, carry-save, and Kogge-Stone adders. The results of FPGA-based hardware modeling and the theoretical parameters of devices calculated using the unit-gate model are compared with state-of-the-art approaches. The unit-gate model showed that the use of the proposed circuits allows us to reduce the area by 17.82%–50.81% and the delay by 1.56%–97.76% for the implementation of the magnitude comparison, and to reduce the delay by 2.80%–95.03% for the implementation of reverse conversion. The FPGA synthesis also showed that the new design has reduced the area and delay by 46.96%–86.80% and 7.15%–47.65%, respectively, for the implementation of magnitude comparison and reduced the delay by 13.63%–81.53% for the implementation of reverse conversion. It is shown that a proposed technique to measure the RNS balance can adequately reflect differences in the RNS performance.

A New FPGA-Based Task Scheduler for Real-Time Systems

This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any need for software intervention. The proposed scheduler utilizes the Earliest-Deadline First (EDF) algorithm and is optimized for multi-core CPUs, capable of executing up to four threads simultaneously. The scheduler also provides support for task suspension, resumption, and enabling inter-task synchronization. The design is based on priority queues, which play a crucial role in decision making and time management. Thanks to the hardware acceleration of the scheduler and the hardware implementation of priority queues, it operates in only two clock cycles, regardless of the number of tasks in the system. The results of the FPGA synthesis, performed on an Intel FPGA device (Cyclone V family), are presented in the paper. The proposed solution was validated through a simplified version of the Universal Verification Methodology (UVM) with millions of test instructions and random deadline and period values.

Mitigation of Critical Delay in the Carry Skip Adders Using FinFET 18nm Technology

In this paper optimization of full adder in 3-dimensional (3-D) using Fin Field Effect Transistor (FinFET) with Gate Diffusion Input (GDI) is proposed to optimize critical delay, power. FinFET technology is more suitable for below 10nm technology process. The major aim of this work is to indemnify significant factor in adder structure i.e. critical delay. Pipelining architecture is enforced to accomplish the objective with the aid of FinFET 18nm technology. The structure is optimized to get the minimum delay confinement. Suggested design needs less logic resources. The outcomes are validated using FPGA synthesis methods. By applying the FinFET technique, we developed adder topology yielding up to 90% performance improvement with respect to delay, power and area compared to the conventional adders. The simulation was carried out with low power cds ff mpt PDK. The study also includes a carry skip adder design for FPGA implementation.

The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research

In this paper we propose μRV32 (MicroRV32) an open source RISC-V platform for education and research. μRV32 integrates several peripherals alongside a configurable 32 bit RISC-V core interconnected with a generic bus system. It supports bare-metal applications as well as the FreeRTOS operating system. Beside an RTL implementation in the modern SpinalHDL language (μRV32 RTL) we also provide a corresponding binary compatible Virtual Prototype (VP) that is implemented in standard compliant SystemC TLM (μRV32 VP). In combination the VP and RTL descriptions pave the way for advanced cross-level methodologies in the RISC-V context. Moreover, based on a readily available open source tool flow, μRV32 RTL can be exported into a Verilog description and simulated with the Verilator tool or synthesized onto an FPGA. The tool flow is very accessible and fully supported under Linux. As part of our experiments we provide a set of ready to use application benchmarks and report execution performance results of μRV32 at the RTL, VP and FPGA level together with a proof-of-concept FPGA synthesis statistic for different processor configurations. We believe that our μRV32 platform is a suitable foundation for further research and education purposes due to its open source nature, accessible toolchain working in Linux and support for small low-priced FPGAs in combination with a solid feature set.

Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-high-speed caches, decoding delay is a key element to consider when selecting an SEC code. Single error correction orthogonal Latin square (SEC OLS) codes have the fastest decoding method. However, these codes impose a higher number of parity check bits compared to other SEC codes. These extra parity bits need to be stored with each data word in cache data array, which increased cache overheads. This may limit their adoption only to applications that can handle such overheads. In this paper, a modified SEC OLS coding scheme is proposed to reduce the number of stored parity check bits. Compared to the original SEC OLS codes, the proposed coding scheme reduces 25% and 31.3% of the stored parity bits when implemented to protect 16-bit and 64-bit data words, respectively. The results of FPGA and ASIC simulation and synthesis show that using the modified SEC to protect 16-bit words can be an attractive solution because it saves a significant amount of parities storage area, while running at a speed comparable to the original SEC OLS code. The implementation of the proposed SEC code to protect 64-bit words may still be suitable for area-sensitive cache applications that can cope with the slightly increased decoding delay.

Efficiency of Priority Queue Architectures in FPGA

This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimized for minimum chip area costs, which leads to lower energy consumption too. The MultiQueue architecture has constant time complexity, constant critical path length and constant latency. Therefore, it is highly predictable and very suitable for real-time systems too. The proposed architecture was verified using a simplified version of UVM and applying millions of instructions with randomly generated input values. Achieved FPGA synthesis results are presented and discussed. These results show significant savings in FPGA Look-Up Tables consumption in comparison to existing solutions. More than 63% of Look-Up Tables can be saved using the MultiQueue architecture instead of the existing priority queues.

PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability

The posit representation for real numbers is an alternative to the ubiquitous IEEE 754 floating-point standard. In this work, we present PERCIVAL, an application-level posit RISC-V core based on CVA6 that can execute all posit instructions, including the quire fused operations. This solves the obstacle encountered by previous works, which only included partial posit support or which had to emulate posits in software. In addition, Xposit, a RISC-V extension for posit instructions is incorporated into LLVM. Therefore, PERCIVAL is the first work that integrates the complete posit instruction set in hardware. These elements allow for the native execution of posit instructions as well as the standard floating-point ones, further permitting the comparison of these representations. FPGA and ASIC synthesis show the hardware cost of implementing 32-bit posits and highlight the significant overhead of including a quire accumulator. However, results show that the quire enables a more accurate execution of dot products. In general matrix multiplications, the accuracy error is reduced up to 4 orders of magnitude. Furthermore, performance comparisons show that these accuracy improvements do not hinder their execution, as posits run as fast as single-precision floats and exhibit better timing than double-precision floats, thus potentially providing an alternative representation.

OPTIMISED META-HEURISTIC QUEUING MODEL IN VLSI PHYSICAL DESIGN

In this paper, the Markov M/D/1/B queuing model that has been created will be discussed. One approach to evaluating the effectiveness of a router is to use a model of a queue that is analogous to the one that we presented above. Having said that, this can be accomplished in a variety of different ways. According to the results of the studies, altering the service rate has a discernible bearing not only on the amount of data the system processes but also on the effectiveness of its operation. For the purpose of demonstrating the viability of our methodology, we built an output-queuing router using FPGA. When utilising this method, it is possible to observe that the queues and the control unit of the router take up an excessive amount of space on the silicon. This is a consequence of the fact that this method is utilised. The difference in effectiveness between a theoretical model and a real prototype is only 2%. This is a very small margin. The study implemented our design on a Xilinx FPGA Vertix II Pro family 100K chips. In the following subsections, we present the router FPGA synthesis results and evaluate its performance.

Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications

No abstract available.

Zigbee Internode Communication and FPGA Synthesis Using Mesh, Star and Cluster Tree Topological Chip

The wireless sensor networks (WSN) research is emerging fast in the areas of agriculture, industry, smart grid communication, smart monitoring, and smart metering. The Zigbee is a wireless network protocol under IEEE 802.15.4 standard, that provides low cost, low power, and lesser delay in data communication over a PAN network. Several sensor nodes are deployed in WSN geospatial domain to communicate with each other. The sensor nodes are the embedded devices used to perform specific applications by sending information in the network through the coordinator node. The coordinator gathers the data, stores into memory, processes it, and route it to the destination node. The Zigbee protocol supports peer-to-peer, star, mesh and cluster tree topology. In the research paper, the hardware chip design for mesh, star, and cluster Zigbee topology is proposed in which 64 nodes are communicating with each other. The chip simulation is performed on Xilinx ISE 14.7 software for 64-bit internode communication and pre-synthesized on Virtex-5 FPGA. The comparative performance of the chip is analyzed with the help of the FPGA device and timing parameters.

Plataforma para Procesamiento de Imágenes sobre SoC FPGA de Xilinx

La aplicación de sistemas de procesamiento de imágenes en edge computing resulta cada vez más atractiva y necesaria. Sin embargo, las exigencias en cuanto a consumo de potencia y alto rendimiento impiden que puedan utilizarse plataformas de procesamiento estándares. En este aspecto, los FPGA son una buena opción para el desarrollo de sistemas de visión computacional a causa de su capacidad de explotación del paralelismo. Por otra parte, el flujo de diseño de las herramientas de síntesis de FPGA actuales admiten lenguajes de alta abstracción como descripciones de entrada, en contraposición a los lenguajes de descripción de hardware. La síntesis de alto nivel (HLS) automatiza el proceso de diseño al transformar la descripción algorítmica en hardware digital mientras se satisfacen las limitaciones del diseño. Sin embargo, a los expertos en procesamiento de imágenes puede resultarles compleja la integración hardware obtenida con el resto de los componentes del sistema, como por ejemplo interfaces de captura y visualización. En este trabajo, se presenta un diseño base para la construcción de aplicaciones de procesamiento de imágenes basada en Zynq. Se proporciona además una metodología que posibilita el desarrollo eficiente de soluciones de procesamiento de imágenes embebidas de manera ágil.

SoC FPGA Accelerated Sub-Optimized Binary Fully Convolutional Neural Network for Robotic Floor Region Segmentation.

In this article, a new Binary Fully Convolutional Neural Network (B-FCN) based on Taguchi method sub-optimization for the segmentation of robotic floor regions, which can precisely distinguish floor regions in complex indoor environments is proposed. This methodology is quite suitable for robot vision in an embedded platform and the segmentation accuracy is up to on average. A total of 6000 training datasets were used to improve the accuracy and reach convergence. On the other hand, to reach real-time computation, a PYNQ FPGA platform with heterogeneous computing acceleration was used to accelerate the proposed B-FCN architecture. Overall, robots would benefit from better navigation and route planning in our approach. The FPGA synthesis of our binarization method indicates an efficient reduction in the BRAM size to 0.5–1% and also GOPS/W is sufficiently high. Notably, the proposed faster architecture is ideal for low power embedded devices that need to solve the shortest path problem, path searching, and motion planning.

An Area-Power Efficient Denoising Hardware Architecture for Real EOG Signal

This paper presents an optimized noise reduction hardware architecture for real electrooculogram (EOG) system. The proposed denoise architecture is developed using differential evolution (DE) algorithm. The algorithm design the filter with fewer sign-power-of-two (SPT) terms to optimize the denoise filter hardware with desired frequency response. The proposed denoise filter architecture with a DE coefficient set uses shift and add approach and is implemented in gate-level Verilog HDL. The real EOG denoise filter’s functionality is checked with Altera DSP Builder and synthesized using Cadence RTL compiler. Both FPGA and ASIC synthesis results are compared with the recently published works. The area and power consumption results show that the proposed filter occupies less area and with low power consumption as compared to the existing architectures.

High Resolution Laser Self-Mixing Displacement Sensor Under Large Variation in Optical Feedback and Speckle

Self-Mixing interferometry (SMI) signal characteristics are highly dependent on both the operating optical regime and target surface. In this paper, a method is proposed to overcome some identified limitations of the even power scalable algorithm (EPSA), such as the required operating regime to be weak feedback. In addition, by using the up-sampling techniques, the number of stages involved in the even-power scalable algorithm can be drastically increased without any data acquisition bandwidth modification. Here, 10 successive stages have been successfully implemented to achieve a theoretical resolution of ${\lambda } _{\sf 0}/ {\sf 2}^{\sf 13}$ . It is further shown that the proposed method can handle and process weak, moderate and strong feedback regime as well as speckle affected SMI signals more efficiently. Lastly, FPGA based hardware emulation of EPSA is also done for later embedded implementation of this high-resolution algorithm. FPGA synthesis results show that the designed system can measure maximum target velocity up to 1.18 m/s while consuming total power of 1.4W.

Design of High Speed FFT using UrdhvaTiryagbhyam Algorithm and Karatsuba Algorithm

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

A Low Complexity Joint Encryption-Modulation Method for IoT Sensor Transceivers

Physical layer encryption (PLE) is a new research trend for securing data in communication systems. However, conventional procedures in works on PLE are of high complexity and degrade the packet error rate (PER) performance of the system. They are therefore not yet suitable for IoT sensors’ transceiver, which has limited power and computational resource. In this paper, we propose a low complexity PLE method named as joint encryption-modulation (JEM) for small transceivers such as IoT sensors. In our JEM method, data is encrypted after modulation to preserve high security. Our JEM method does not make change the constellation of the modulation after encryption; therefore, the encryption does not degrade PER performance of the system as the conventional works do. Furthermore, the encryption is performed by XOR gates and multiplexers only. It is, therefore, low complexity. Our experiment results show that the JEM method improves about 3 dB of PER performance as compared with that of conventional works. JEM method can support multiple modulation types such as BPSK, QPSK, 16-256 QAM within a small hardware cost. Compared with conventional works, JEM’s hardware resource is reduced by 87.5% in terms of FPGA synthesis and 86.5% in terms of the ASIC circuit. ASIC static power consumption of JEM is reduced by 80.6%.

Novel efficient on-chip task scheduler for multi-core hard real-time systems

This article presents an efficient hardware architecture of EDF-based task scheduler, which is suitable for hard real-time systems due to the constant response time of the scheduler. The proposed scheduler contains a queue of ready tasks that is based on a new MIN/MAX queue architecture called Heap Queue, which is inspired by Shift Registers, Systolic Arrays, heapsort algorithm, the Rocket Queue architecture and dual-port RAMs. The instructions of the proposed scheduler have throughput of one instruction per two clock cycles regardless of the actual number of tasks managed by the scheduler, and regardless of the scheduler capacity. The developed task scheduler is optimized for low chip area costs, which leads to lower energy consumption. The Heap Queue-based architecture has constant time complexity due to two clock-cycle response time of the instructions and therefore, the architecture is highly deterministic. The scheduler supports CPUs that can execute 1, 2 or 4 tasks simultaneously, and contains an implementation of clever and efficient logic that can handle conflicts caused by the fact that the scheduler is used by all CPU cores at the same time. The proposed scheduler was verified through SystemVerilog UVM-like simulations that applied billions of randomly generated test instructions. Achieved ASIC (28 nm) and FPGA synthesis results are presented and compared. More than 86% of the chip area and 93% of the total power consumption can be saved if Heap Queue architecture is used in hardware implementations of EDF algorithm. Advantages and disadvantages of the proposed task scheduler are discussed through the comparison to the existing solutions.

A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding.

This paper presents a hardware efficient pixel-domain just-noticeable difference (JND) model and its hardware architecture implemented on an FPGA. This JND model architecture is further proposed to be part of a low complexity pixel-domain perceptual image coding architecture, which is based on downsampling and predictive coding. The downsampling is performed adaptively on the input image based on regions-of-interest (ROIs) identified by measuring the downsampling distortions against the visibility thresholds given by the JND model. The coding error at any pixel location can be guaranteed to be within the corresponding JND threshold in order to obtain excellent visual quality. Experimental results show the improved accuracy of the proposed JND model in estimating visual redundancies compared with classic JND models published earlier. Compression experiments demonstrate improved rate-distortion performance and visual quality over JPEG-LS as well as reduced compressed bit rates compared with other standard codecs such as JPEG 2000 at the same peak signal-to-perceptible-noise ratio (PSPNR). FPGA synthesis results targeting a mid-range device show very moderate hardware resource requirements and over 100 Megapixel/s throughput of both the JND model and the perceptual encoder.

A Novel Nonlinear Function Evaluation Approach for Efficient FPGA Mapping of Neuron and Synaptic Plasticity Models.

Efficient hardware realization of spiking neural networks is of great significance in a wide variety of applications, such as high-speed modeling and simulation of large-scale neural systems. Exploiting the key features of FPGAs, this paper presents a novel nonlinear function evaluation approach, based on an effective uniform piecewise linear segmentation method, to efficiently approximate the nonlinear terms of neuron and synaptic plasticity models targeting low-cost digital implementation. The proposed approach takes advantage of a high-speed and extremely simple segment address encoder unit regardless of the number of segments, and therefore is capable of accurately approximating a given nonlinear function with a large number of straight lines. In addition, this approach can be efficiently mapped into FPGAs with minimal hardware cost. To investigate the application of the proposed nonlinear function evaluation approach in low-cost neuromorphic circuit design, it is applied to four case studies: the Izhikevich and FitzHugh-Nagumo neuron models as 2-dimensional case studies, the Hindmarsh-Rose neuron model as a relatively complex 3-dimensional model containing two nonlinear terms, and a calcium-based synaptic plasticity model capable of producing various STDP curves. Simulation and FPGA synthesis results demonstrate that the hardware proposed for each case study is capable of producing various responses remarkably similar to the original model and significantly outperforms the previously published counterparts in terms of resource utilization and maximum clock frequency.