FPGA Mezzanine Card Research Articles

Design and Implementation of an MIPI A-PHY Retransmission Layer for Automotive Applications

Recently, with the development of automobile technologies such as advanced driver assistance systems (ADASs), the performance and number of cameras and displays required for a vehicle have significantly increased. Therefore, the need for in-vehicle high-speed data transmission has increased, but there is difficulty in handling the required high-speed data transmission in existing in-vehicle networks. The MIPI A-PHY interface for automobiles has been proposed as a new standard to solve this issue. To ensure data transmission in noisy automotive environments, the A-PHY interface contains an added retransmission (RTS) layer within the new physical layer. In this paper, we propose and design in detail the structure of an RTS layer presented in the standard A-PHY interface. The proposed RTS layer was designed to satisfy the RTS specification of the MIPI A-PHY standard and was verified through simulations. Moreover, the A-PHY SerDes environment was configured in an FPGA using a Xilinx KC705 FPGA development board and an FPGA Mezzanine Card (FMC) loopback module, and RTS layer operation was verified through the process of transmitting video data to the A-Packet. The A-PHY interface with the RTS layer designed on the FPGA uses 3924 LUTs, 2019 registers, and 132 block memories and operates at a maximum speed of 200 MHz. In addition, as a result of designing the A-PHY interface as an ASIC implementation using the Synopsys SAED 28 nm process, the number of logic gates is 25 K, the chip area is 0.40 mm2, and the maximum operating speed is 200 MHz.

The MicroTCA.4 Fast Control and Processing Board for Generic Control and Data Acquisition Applications in HEP Experiments

The MicroTCA.4 Fast Control and Processing board (u4FCP) is an FPGA-based double-width MicroTCA.4 compatible Advanced Mezzanine Card (AMC) for generic control and data acquisition applications in High-Energy Physics (HEP) experiments. Built around the Xilinx Kintex UltraScale+ FPGA, the u4FCP provides users with a platform which has access to on-board FPGA Mezzanine Card (FMC) sockets with an array of configurable I/O and high-speed links up to 100 Gbps. In addition, the rear transition module (RTM) allows separation of processing and I/O functionality with the Kintex -7 FPGA and more FMC sockets. The increased processing capacity and area on the RTM allow a significant increase in the amount of FPGA logic and I/O connections. The on-going R&D effort carried out on applications in HEP experiments is presented.

Design of a MAPS readout electronics prototype for BESIII inner tracker

The spatial resolution and the reconstruction efficiency of the main drift chamber of the Beijing Spectrometer III has degraded after more than nine years of operation. An improved new inner drift chamber has been constructed to replace the old chamber in case of the radiation damage. A monolithic active pixel sensor (MAPS) based detector prototype is selected as one of the prototype schemes for the inner chamber upgrade. Design a set of MAPS readout electronics system for the inner drift chamber upgrade. This system can verify the function and performance of the selected MAPS chip and discover the matters needing attention when designing large-scale detectors. The electronics system design is composed of three parts. The first part is flexible printed circuit boards (PCBs) assembled with the MAPS chips. The second part is digital readout boards, which are connected to the flexible PCBs via FPGA mezzanine card cables. The digital readout board realizes the configuration of the MAPS chip register, receives and processes the data output by the MAPS chip, and transfers the processed data to the DAQ device. The third part includes a readout control board and two fan-out boards that used to separately fan out the trigger signal and the start signal to all the digital readout boards. A MAPS readout electronics system consisting of five MAPS based detector prototypes is designed. The system can work stably under the electron beam experimental conditions with a frequency up to 2 kHz and energy ranging from 1 to 5 GeV. The system detection efficiency of the electron beam is $$\sim 95\%$$, and the spatial resolution is $$\sim 5.3\, \upmu \hbox {m}$$ at electron energies of 1 GeV. The design of the electronics system meets the requirements for verifying the performance of the MAPS chips and the technical feasibility of the detector structure.

A versatile small form factor twisted-pair TFC FMC for MTCA AMCs

In continuous readout systems of particle physics experiments, the provision of a common clock and time reference and the distribution of critical low latency messages to the processing and fronted layers of the readout are crucial tasks. In the context of the Compressed Baryonic Matter (CBM) experiment, a versatile small form factor Timing and Fast-Control (TFC) interfacing FPGA Mezzanine Card (FMC) was developed, offering bidirectional twisted-pair (TP) links for the communication between TFC nodes. Also a versatile clocking including voltage controlled oscillators and a connection to the telecommunication clock lines of mTCA crates are available. Being designed for both TFC Master and Slaves, the card allows rapid system developments without additional Slave hardware circuits. Measurements show that it is possible to transmit over cable lengths of 25 m at a rate of 240 Mbit/s for all data channels simultaneously. A TFC Master-Slave system using two of these cards can be synchronized with a precision of ±10 ps to an user-defined phase setpoint.

The Triple GEM Detector Control System for CMS forward muon spectrometer upgrade

The CMS experiment at LHC will upgrade its forward muon spectrometer by incorporating Triple-GEM detectors. This upgrade referred to as GEM Endcap (GE1/1), consists of adding two back-to-back Triple-GEM detectors in front of the existing Cathode Strip Chambers (CSC) in the innermost ring of the endcap muon spectrometer. Before the full installation of 144 detectors in 2019–2020, CMS will first install ten single chamber prototypes during the early 2017. This pre-installation is referred as the slice test. These ten detectors will be read-out by VFAT2 chips [1]. On-detector there is also a FPGA mezzanine card which sends VFAT2 data optically to the μTCA back-end electronics. The correct and safe operation of the GEM system requires a sophisticated and powerful online Detector Control System, able to monitor and control many heterogeneous hardware devices. The DCS system developed for the slice test has been tested with CMS Triple-GEM detectors in the laboratory. In this paper we describe the newly developed DCS system and present the first results obtained in the GEM assembly and quality assurance laboratory.

Development of an ADC radiation tolerance characterization system for the upgrade of the ATLAS LAr calorimeter**Supported by the U. S. Department of Energy (DE-SC001270)

ATLAS LAr calorimeter will undergo its Phase-I upgrade during the long shutdown (LS2) in 2018, and a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multi-channel high-speed ADCs have been selected as possible backups of the radiation tolerant ADC ASICs for the LTDB. To evaluate the radiation tolerance of these backup commercial ADCs, we developed an ADC radiation tolerance characterization system, which includes the ADC boards, data acquisition (DAQ) board, signal generator, external power supplies and a host computer. The ADC board is custom designed for different ADCs, with ADC drivers and clock distribution circuits integrated on board. The Xilinx ZC706 FPGA development board is used as a DAQ board. The data from the ADC are routed to the FPGA through the FMC (FPGA Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then transmitted to the host computer through the Gigabit Ethernet. A software program has been developed with Python, and all the commands are sent to the DAQ board through Gigabit Ethernet by this program. Two ADC boards have been designed for the ADC, ADS52J90 from Texas Instruments and AD9249 from Analog Devices respectively. TID tests for both ADCs have been performed at BNL, and an SEE test for the ADS52J90 has been performed at Massachusetts General Hospital (MGH). Test results have been analyzed and presented. The test results demonstrate that this test system is very versatile, and works well for the radiation tolerance characterization of commercial multi-channel high-speed ADCs for the upgrade of the ATLAS LAr calorimeter. It is applicable to other collider physics experiments where radiation tolerance is required as well.

SPIDR, a general-purpose readout system for pixel ASICs

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a “soft core” CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

Development of a high data-throughput ADC board for the PROMETEO portable test-bench for the upgraded front-end electronics of the ATLAS TileCal

The Large Hadron Collider (LHC) is preparing for a major Phase-II upgrade scheduled for 2022 [1]. The upgrade will require a complete redesign of both on- and off-detector electronics systems in the ATLAS Tile hadron Calorimeter (TileCal) [2]. The PROMETEO (A Portable ReadOut ModulE for Tilecal ElectrOnics) stand-alone test-bench system is currently in development and will be used for the certification and quality checks of the new front- end electronics. The Prometeo is designed to read in digitized samples from 12 channels simultaneously at the bunch crossing frequency while accessing quality of information in realtime. The main board used for the design is a Xilinx VC707 evaluation board with a dual QSFP+ FMC (FPGA Mezzanine Card) module for read-out and control of the front-end electronics. All other functions are provided by a HV board, LED board and a 16 channel ADC daughter board. The paper relates to the development and testing of the ADC board that will be used in the new Prometeo system.

The FC7 AMC for generic DAQ & control applications in CMS

The FC7 is a flexible, μTCA compatible Advanced Mezzanine Card (AMC) for generic data acquisition/control applications. Built around the Xilinx Kintex-7 FPGA, the FC7 provides developers with a platform which has access to a large array of configurable I/O, primarily delivered from on-board FPGA Mezzanine Card (FMC) sockets. Targeting users of high-speed optical links in high energy physics experiments, the board is capable of driving and receiving links up to 10 Gbps. This paper presents test results from the first set of pre-production prototypes and reports on FC7 uses and applications towards upgrades in CMS.

Development of 3He LPSDs and read-out system for the SANS spectrometer at CPHS

The Compact Pulsed Hadron Source (CPHS) is a 13-MeV proton-linac-driven neutron source under construction in Tsinghua University. Time-of-flight (TOF) small-angle neutron scattering (SANS) spectrometer is one of the first instruments to be built. It is designed to use linear position-sensitive detectors (LPSDs) of 3He gas proportional counters to cover a 1m×1m area. Prototypical LPSDs (Φ=12mm, L=1m) have been made and read-out system is developed based on charge division. This work describes the in-house fabrication of the prototypical LPSDs and design of the read-out system including front-end electronics and data acquisition (DAQ) system. Key factors of the front-end electronics are studied and optimized with PSPICE simulation. DAQ system is designed based on VME bus architecture and FPGA Mezzanine Card (FMC) standard with high flexibility and extendibility. Preliminary experiments are carried out and the results are present and discussed.

Development of an ATCA IPMI controller mezzanine board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade

In the context of the LHC upgrade, we develop a new Read Out Driver (ROD) for the ATLAS Liquid Argon (LAr) community. ATCA and μTCA (Advanced/Micro Telecom Computing Architecture) is becoming a standard in high energy physics and a strong candidate to be used for boards and crates. We work to master ATCA and to integrate a large number of high speed links (96 links at 8.5 Gbps) on a ROD evaluation ATCA board. A versatile ATCA IPMI controller for ATCA boards which is FPGA Mezzanine Card (FMC) compliant has been developed to control the ROD evaluation board.